公开(公告)号：US20240264374A1

公开(公告)日：2024-08-08

申请号：US18105304

申请日：2023-02-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G02B6/122 ,  G02B6/136 ,  H01L23/38 ,  H01L23/48

CPC classification number: G02B6/1228 ,  G02B6/136 ,  H01L23/38 ,  H01L23/481 ,  G02B2006/12121

Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a substrate including a cavity, a thermoelectric device inside the cavity, and a chip disposed inside the cavity adjacent to the thermoelectric device. The thermoelectric device includes a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US12046633B2

公开(公告)日：2024-07-23

申请号：US17157269

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Johnatan A. Kantarovsky ,  Vibhor Jain

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/764 ,  H01L27/06 ,  H01L27/07 ,  H01L29/08

CPC classification number: H01L29/0657 ,  H01L21/308 ,  H01L21/764 ,  H01L27/0635 ,  H01L27/0755 ,  H01L29/0653 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US20240243175A1

公开(公告)日：2024-07-18

申请号：US18098188

申请日：2023-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

公开(公告)号：US12040388B2

公开(公告)日：2024-07-16

申请号：US17525634

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Judson R. Holt ,  Alexander Derrickson

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/6625

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

公开(公告)号：US20240234448A1

公开(公告)日：2024-07-11

申请号：US18151509

申请日：2023-01-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： DAVID PRITCHARD ,  HONG YU ,  ZHIXING ZHAO

IPC: H01L27/13 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/13 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.

公开(公告)号：US20240234346A1

公开(公告)日：2024-07-11

申请号：US18095156

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. LEVY ,  Brett T. CUCCI ,  Spencer H. PORTER ,  Santosh SHARMA

IPC: H01L23/58 ,  H01L23/31 ,  H01L23/532 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/585 ,  H01L23/3178 ,  H01L23/53295 ,  H01L29/0657 ,  H01L29/66462 ,  H01L29/7786 ,  H01L23/291

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures and methods of manufacture. The structure includes: a semiconductor substrate; a channel layer above the semiconductor substrate; a trench within the channel layer, extending to the semiconductor substrate; and a moisture barrier layer lining sidewalls and a bottom surface of the trench.

公开(公告)号：US20240221810A1

公开(公告)日：2024-07-04

申请号：US18607725

申请日：2024-03-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

公开(公告)号：US12027553B2

公开(公告)日：2024-07-02

申请号：US17896401

申请日：2022-08-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Vibhor Jain ,  Alvin J. Joseph ,  Steven M. Shank

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors with buried airgap mirror reflectors. The structure includes a photodetector and at least one airgap in a substrate under the photodetector.

公开(公告)号：US20240210621A1

公开(公告)日：2024-06-27

申请号：US18597173

申请日：2024-03-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brett T. Cucci ,  Yusheng Bian ,  Abdelsalam Aboketaf ,  Edward W. Kiewra

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/125 ,  G02B6/132

CPC classification number: G02B6/1228 ,  G02B6/1223 ,  G02B6/125 ,  G02B6/132 ,  G02B2006/12061 ,  G02B2006/12147 ,  G02B6/1225

Abstract: Disclosed are embodiments of a photonic integrated circuit (PIC) structure with a waveguide core having tapered sidewall liner(s) (e.g., symmetric tapered sidewall liners on opposing sides of a waveguide core, asymmetric tapered sidewall liners on opposing sides of a waveguide core, or a tapered sidewall liner on one side of a waveguide core). In some embodiments, the tapered sidewall liner(s) and waveguide core have different refractive indices. In an exemplary embodiment, the waveguide core is a first material (e.g., silicon) and the tapered sidewall liner(s) is/are a second material (e.g., silicon nitride) with a smaller refractive index than the first material. In another exemplary embodiment, the waveguide core is a first compound and the tapered sidewall liner(s) is/are a second compound with the same elements (e.g., silicon and nitrogen) as the first compound but with a smaller refractive index. Also disclosed are method embodiments for forming such a PIC structure.