公开(公告)号：US10103731B2

公开(公告)日：2018-10-16

申请号：US15688527

申请日：2017-08-28

申请人： Integrated Silicon Solution, Inc.

发明人： Kim C. Hardee

IPC分类号： H03K19/00 ,  H03K5/24 ,  H03K19/0175 ,  G11C29/50 ,  H03K19/0185

摘要： Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.

公开(公告)号：US09967932B1

公开(公告)日：2018-05-08

申请号：US15629112

申请日：2017-06-21

申请人： Integrated Silicon Solution, Inc.

发明人： ChungTing Yao

IPC分类号： H05B33/08

CPC分类号： H05B33/0815

摘要： An LED controller for a multiple LED channel system using PWM method for LED dimming function incorporates a digital dimming control circuit to generate the PWM signals for driving the LED channels to spread out or cancel out the power supply transients generated by the LED transient current during PWM modulation for dimming operation. The digital dimming control circuit implements a power supply transient reduction method whereby the active period of the PWM signals for some of the LED channels are shifted within the switching cycle to align at least some of the rising signal edges with some of the falling signal edges so as to cancel out the voltage transients on the LED power rails generated at the signal transitions. Furthermore, the rising and falling signal edges that are not lined up are spread out through the PWM switching cycle so that the power supply transients are spread out.

公开(公告)号：US09880901B2

公开(公告)日：2018-01-30

申请号：US15354773

申请日：2016-11-17

申请人： Integrated Silicon Solution, Inc.

发明人： Lyn R. Zastrow

IPC分类号： H03M13/00 ,  G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G06F11/1076 ,  G11C29/52

摘要： A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring modifications to the memory controller used to control and communicate with the memory device.

公开(公告)号：US09780785B2

公开(公告)日：2017-10-03

申请号：US15226488

申请日：2016-08-02

申请人： Integrated Silicon Solution, Inc.

发明人： Kim C. Hardee

IPC分类号： H03K19/00 ,  H03K5/24 ,  H03K19/0175 ,  G11C29/50 ,  H03K19/0185

CPC分类号： H03K19/0005 ,  G11C7/1057 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/5004 ,  G11C2207/2254 ,  H03K5/24 ,  H03K19/017545 ,  H03K19/017581 ,  H03K19/018557 ,  H03K19/018585 ,  H03K2217/94031

摘要： Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance.

公开(公告)号：US09543016B1

公开(公告)日：2017-01-10

申请号：US14869820

申请日：2015-09-29

申请人： Integrated Silicon Solution, Inc.

发明人： Kyoung Chon Jin

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC分类号： G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30 ,  G11C16/345 ,  G11C16/3459 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/7884

摘要： A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

摘要翻译： 用于PMOS多时间可编程（MTP）闪存器件的编程方法将选择栅极晶体管偏置到恒定的漏极电流电平，并将控制栅极偏置电压从低电压电平扫描到高电压电平，同时保持电池电流周围 预定的电池电流限制电平。 以这种方式，PMOS MTP闪存器件可以使用热载流子注入（HCI）实现低功率和高速程序。 本发明的编程方法能够实现PMOS MTP闪存单元的多位编程，从而提高编程速度，同时保持低功耗。

公开(公告)号：US09529667B2

公开(公告)日：2016-12-27

申请号：US14279113

申请日：2014-05-15

申请人： Integrated Silicon Solution, Inc.

发明人： Lyn R. Zastrow

IPC分类号： G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/1076

摘要： A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.

摘要翻译： 实现误差校正的存储器件中的方法包括将纠错事件寄存器设置为第一值; 响应于存储器地址访问第一存储器阵列中的存储器位置; 从所述第一存储器阵列中的所访问的存储器位置检索存储的存储器数据，并从所述第二存储器阵列检索对应于所访问的存储器位置的纠错校验位; 使用检索到的校验位检查检索到的存储器数据的位错误; 响应于在所检索的存储器数据中检测到位误差，使用所检索的校验位产生校正的存储器数据，并且确定纠错事件信号; 并且响应于纠错事件信号被断言，将纠错事件寄存器设置为第二值。

公开(公告)号：US09496046B1

公开(公告)日：2016-11-15

申请号：US14826635

申请日：2015-08-14

申请人： Integrated Silicon Solution, Inc.

发明人： Kyoung Chon Jin

IPC分类号： G11C7/00 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24

CPC分类号： G11C16/28 ,  G11C16/24 ,  G11C16/32

摘要： A flash memory device implements a sequential read method using overlapping read cycles to initiate the bit-line precharge and equalization operation for a next memory cell address prior to the completion of the read cycle of the current memory cell address. More specifically, the sequential read method implements overlapping read cycle where the bit-line precharge and equalization operation is started for a memory cell of the next address while the memory cell of the current address is being read out. In this manner, the read speed for the sequential read operation of the flash memory device is improved. In some embodiments, the memory cell array for each input-output (I/O) of the flash memory device is partitioned into two sub-banks to further reduce the read cycle time by enabling early activation of the word-line for the next sub-bank.

摘要翻译： 快闪存储器件在使用当前存储器单元地址的读取周期完成之前，使用重叠的读周期来执行顺序读取方法以启动下一个存储器单元地址的位线预充电和均衡操作。 更具体地，顺序读取方法实现重叠的读取周期，其中当读取当前地址的存储单元时，对下一个地址的存储单元开始位线预充电和均衡操作。 以这种方式，提高了闪速存储器件的顺序读取操作的读取速度。 在一些实施例中，用于闪速存储器件的每个输入输出（I / O）的存储单元阵列被划分成两个子库，以通过使得下一个子字的字线的早期激活来进一步减少读周期时间 -银行。

公开(公告)号：US09324426B2

公开(公告)日：2016-04-26

申请号：US14293982

申请日：2014-06-02

申请人： Integrated Silicon Solution, Inc.

发明人： Seong Jun Jang ,  Justin Kim ,  Geun-Young Park

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2213/16 ,  G11C2213/79 ,  G11C2213/82

摘要： A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

摘要翻译： 电阻式存储器件中的方法包括配置共享相同位线和相同源极线的阵列中的两个或更多个存储器单元并联操作为合并存储器单元; 响应于写入数据对合并的存储单元的电阻进行编程，同时对被合并的存储单元中的两个或多个电阻存储单元的电阻进行编程; 并且读取合并的存储单元的编程电阻值，同时读取合并的存储单元中的两个或多个存储单元的编程电阻。

公开(公告)号：US09280418B2

公开(公告)日：2016-03-08

申请号：US13957251

申请日：2013-08-01

申请人： Integrated Silicon Solution, Inc.

发明人： Wing-Hin Kao ,  Jongsik Na

IPC分类号： G06F12/02 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.

摘要翻译： 使用纠错码（ECC）的存储器件实现存储器阵列并行读写方法，以减少存储ECC校验位所需的存储开销。 存储器阵列并行读写方法将输入地址和数据分别存储到串并行并行输出（SIPO）地址寄存器和写数据寄存器中。 当SIPO寄存器满时，存储的数据被并行写入存储单元。 为存储在写入数据寄存器中的并行输入数据块生成ECC校验位。 在读取操作期间，并行地从存储器单元读取对应于读取地址的读出数据块，并将其存储在读取寄存器中。 在选择所需输出数据以输出之前，对读出数据块执行ECC校正。

公开(公告)号：US20150348624A1

公开(公告)日：2015-12-03

申请号：US14293982

申请日：2014-06-02

申请人： Integrated Silicon Solution, Inc.

发明人： Seong Jun Jang ,  Justin Kim ,  Geun-Young Park

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0088 ,  G11C2213/16 ,  G11C2213/79 ,  G11C2213/82

摘要： A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

摘要翻译： 电阻式存储器件中的方法包括配置共享相同位线和相同源极线的阵列中的两个或更多个存储器单元并联操作为合并存储器单元; 响应于写入数据对合并的存储单元的电阻进行编程，同时对被合并的存储单元中的两个或多个电阻存储单元的电阻进行编程; 并且读取合并的存储单元的编程电阻值，同时读取合并的存储单元中的两个或多个存储单元的编程电阻。