中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

127 records (took 0.023 seconds)

    DETECTION AND ESTIMATION OF NARROWBAND INTERFERENCE BY MATRIX MULTIPLICATION
    31.
    发明申请
    DETECTION AND ESTIMATION OF NARROWBAND INTERFERENCE BY MATRIX MULTIPLICATION 有权
    通过矩阵多项式检测和估计窄带干扰

    公开(公告)号：US20130215949A1

    公开(公告)日：2013-08-22

    申请号：US13854675

    申请日：2013-04-01

    Applicant: Applied Micro Circuits Corporation

    Inventor： Dariush DABIRI

    IPC: H04B3/46

    CPC classification number: H04B3/46 ,  H04B17/345

    Abstract: One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference.

    Abstract translation: 一个或多个处理单元被编程为在信号的频域表示中从M个音调中选择一组音调，其包括至少最强音（相对于背景噪声）和与其相邻的音调。 在信号的频域表示中的M个复数中，识别一组复数，并将其表示为对应于所选择的一组音调的向量Z。 然后将向量Z乘以预定的矩阵G的每个M列，以标识Z中的子分辨率最大值。由Z和G的矢量相乘产生的M个乘积至少用于确定和存储在存储器中 一个或两个：（A）指示信号中存在或不存在窄带干扰的标志; 和（B）对窄带干扰的频率的估计。

    Resolving interaction between channel estimation and timing recovery
    32.
    发明授权
    Resolving interaction between channel estimation and timing recovery 有权

    公开(公告)号：US09882710B2

    公开(公告)日：2018-01-30

    申请号：US15191229

    申请日：2016-06-23

    Applicant: Applied Micro Circuits Corporation

    Inventor： Yehuda Azenkot ,  Bart R. Zeydel

    IPC: H04L7/04 ,  H04L7/00 ,  H04L7/033

    CPC classification number: H04L7/04 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03

    Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

    Mapping a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals
    36.
    发明授权
    Mapping a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals 有权
    映射多个信号以产生包括比与多个信号相关联的数据速率更高的数据速率的组合信号

    公开(公告)号：US09590756B2

    公开(公告)日：2017-03-07

    申请号：US14027518

    申请日：2013-09-16

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Francesco Caggioni ,  Dimitrios Giannakopoulos

    IPC: H04J14/08 ,  H04J3/16 ,  H04L12/26

    CPC classification number: H04J3/1664

    Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.

    Abstract translation: 各种方面提供用于映射多个信号以生成组合信号。 聚合组件被配置为基于与多个信号相关联的映射数据来生成包括比与多个信号相关联的数据速率更高的数据速率的组合信号。 聚合组件包括映射器组件。 映射器组件被配置用于基于与通用映射过程相关联的映射分布模式来生成映射数据。 在一方面，解聚合组件被配置为从以组合信号的数据速率发送的伪信号中恢复多个信号。 在另一方面，解聚合组件包括解映射器组件，其被配置为基于与通用映射过程相关联的映射分布模式来对映射的数据进行解映射。

    High frequency voltage supply monitor
    37.
    发明授权
    High frequency voltage supply monitor 有权
    高频电压监视器

    公开(公告)号：US09568511B2

    公开(公告)日：2017-02-14

    申请号：US14208408

    申请日：2014-03-13

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Luca Ravezzi ,  Qawi Harvard ,  Hamid Partovi

    IPC: G01R19/165 ,  G01R19/00 ,  G06F1/26

    CPC classification number: G01R19/16552 ,  G01R19/0007 ,  G06F1/26 ,  G06F1/305

    Abstract: Various aspects provide a high frequency voltage supply monitor capable of monitoring high frequency variations of the voltage supply inside a microelectronic circuit substantially in real time. The voltage supply monitor can comprise a differential amplifier circuit having a substantially constant gain over a wide bandwidth, allowing the supply voltage variations to be amplified according to a known gain under a wide range of conditions. The amplified signal can then be sent to an output port for monitoring and measurement by an external display device.

    Abstract translation: 各种方面提供了一种能够基本上实时地监测微电子电路内的电压供应的高频变化的高频电压监视器。 电压监视器可以包括在宽带宽上具有基本上恒定的增益的差分放大器电路，从而允许根据在宽范围条件下的已知增益放大电源电压变化。 放大的信号然后可以被发送到输出端口，用于由外部显示装置进行监视和测量。

    CLOCK PHASE ADAPTATION FOR PRECURSOR ISI REDUCTION
    38.
    发明申请
    CLOCK PHASE ADAPTATION FOR PRECURSOR ISI REDUCTION 有权
    用于前驱体ISI减少的时钟相位适应

    公开(公告)号：US20160234043A1

    公开(公告)日：2016-08-11

    申请号：US14619952

    申请日：2015-02-11

    Applicant: Applied Micro Circuits Corporation

    Inventor： Yehuda AZENKOT ,  Guy Jacque FORTIER

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03019 ,  H04L7/0025 ,  H04L7/0062 ,  H04L2025/03592

    Abstract: Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(−1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.

    Abstract translation: 用于使用数字电路设计具有时变先驱信道响应的通信信道的前体ISI的系统和方法。 在接收机中使用相位自适应电路，并且被配置为响应于输入信号并且基于当前前置信道响应产生相位控制信号。 相位控制信号将恢复的时钟的相移控制在h（-1）处的前体ISI最小化的位置。 相位控制信号对应于通过数字最小均方（LMS）处理获得的“前馈均衡（FFE）第一抽头权重”。

    Discrete time compensation mechanisms
    39.
    发明授权
    Discrete time compensation mechanisms 有权
    离散时间补偿机制

    公开(公告)号：US09344209B2

    公开(公告)日：2016-05-17

    申请号：US14016534

    申请日：2013-09-03

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Stacy Nichols ,  Sameer Gandhi ,  Burt Christian

    IPC: H04J3/06

    CPC classification number: H04J3/0697 ,  H04J3/0661

    Abstract: Discrete time compensation mechanisms include a channel component configured for determining which channel of a plurality of channels to process time slots of sampled data that are time stamped in a discrete time and processing the time slots of the sampled data to the plurality of channels. A common channel clock component is configured for time stamping the time slots of the sampled data in the discrete time domain that is faster than a non-discrete reference time stamp of continuous data from which the time slots are sampled from and for processing the sampled data through the plurality of channels faster than the continuous data is being received. Compensations for one or more gaps are generated based on a set of predetermined criteria and a corrected time stamp is applied to the sampled data for processing among different processing channels.

    Abstract translation: 离散时间补偿机制包括被配置用于确定多个信道的哪个信道处理在离散时间中被时间戳的采样数据的时隙并且将采样数据的时隙处理到多个信道的信道分量。 公共通道时钟部件被配置用于对离散时域中的采样数据的时隙进行时间戳，该时隙比连续数据的非离散参考时间戳更快，从该数据的时隙中抽取时隙并从处理采样数据 通过多个信道比正在接收的连续数据更快。 基于一组预定标准产生一个或多个间隙的补偿，并且将校正的时间戳应用于采样数据，以在不同的处理通道之间进行处理。

    Programmable gain amplifier with controlled gain steps
    40.
    发明授权
    Programmable gain amplifier with controlled gain steps 有权
    具有受控增益步长的可编程增益放大器

    公开(公告)号：US09325287B2

    公开(公告)日：2016-04-26

    申请号：US14162896

    申请日：2014-01-24

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Nanda Govind Jayaraman ,  Tarun Gupta

    IPC: H03F3/45 ,  H03G3/30

    CPC classification number: H03G3/30 ,  H03G1/0029

    Abstract: Provided is a programmable gain amplifier that includes controlled gain steps that dynamically control an output voltage in real-time. The programmable gain amplifier includes a first transistor and a second transistor that includes respective control ports, input ports, and output ports. The programmable gain amplifier also includes a resistor connected to the output ports of the transistors. Further, at least a third transistor is connected to the output ports, in parallel with the resistor. On applying a control voltage to the third transistor and applying an input voltage to the first control port, the second control port is selectively modified by the control voltage to produce a desired output at the first input port and the second input port.

    Abstract translation: 提供了一种可编程增益放大器，其包括可实时动态地控制输出电压的受控增益步长。 可编程增益放大器包括第一晶体管和第二晶体管，其包括相应的控制端口，输入端口和输出端口。 可编程增益放大器还包括连接到晶体管的输出端口的电阻器。 此外，至少第三晶体管与电阻器并联连接到输出端口。 在对第三晶体管施加控制电压并向第一控制端口施加输入电压时，通过控制电压选择性地修改第二控制端口，以在第一输入端口和第二输入端口产生期望的输出。

Patent Agency Ranking