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    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods
    32.
    发明授权
    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
    异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法

    公开(公告)号：US07429504B2

    公开(公告)日：2008-09-30

    申请号：US11080737

    申请日：2005-03-15

    Applicant: Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    Inventor： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC: H01L21/764 ,  H01L31/0336

    CPC classification number: H01L29/0653 ,  H01L29/78

    Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

    Abstract translation: 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

    Fin field effect transistors including epitaxial fins
    33.
    发明授权
    Fin field effect transistors including epitaxial fins 有权
    Fin场效应晶体管包括外延鳍片

    公开(公告)号：US07394117B2

    公开(公告)日：2008-07-01

    申请号：US11622103

    申请日：2007-01-11

    Applicant: In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    Inventor： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC: H01L29/34

    CPC classification number: H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Finfets having first and second gates of different resistivities
    37.
    发明授权
    Finfets having first and second gates of different resistivities 有权
    Finfets具有不同电阻率的第一和第二门

    公开(公告)号：US07268396B2

    公开(公告)日：2007-09-11

    申请号：US10937246

    申请日：2004-09-09

    Applicant: Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    Inventor： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    IPC: H01L29/772

    CPC classification number: H01L29/785 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/66795

    Abstract: A fin field effect transistor (FinFET) includes a first gate and a second gate. The first gate has a vertical part that is defined by sidewalls of a silicon fin and sidewalls of a capping pattern disposed on the silicon fin and a horizontal part horizontally extends from the vertical part. The second gate is made of a low-resistivity material and is in direct contact with the horizontal part of the first gate. A channel may be controlled due to the first gate, and a device operating speed may be enhanced due to the second gate. Related fabrication methods also are described.

    Abstract translation: 鳍状场效应晶体管（FinFET）包括第一栅极和第二栅极。 第一栅极具有由硅翅片的侧壁和设置在硅片上的封盖图案的侧壁限定的垂直部分，并且水平部分从垂直部分水平延伸。 第二栅极由低电阻率材料制成，并与第一栅极的水平部分直接接触。 由于第一门可以控制通道，并且由于第二门可能会增强设备运行速度。 还描述了相关的制造方法。

    FIN FIELD EFFECT TRANSISTORS INCLUDING EPITAXIAL FINS
    38.
    发明申请
    FIN FIELD EFFECT TRANSISTORS INCLUDING EPITAXIAL FINS 有权
    包括外源性FINS的FIN场效应晶体管

    公开(公告)号：US20070111439A1

    公开(公告)日：2007-05-17

    申请号：US11622103

    申请日：2007-01-11

    Applicant: In Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    Inventor： In Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC: H01L21/8242 ,  H01L29/76

    CPC classification number: H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比活性区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Methods of fabricating fin field effect transistors
    39.
    发明授权
    Methods of fabricating fin field effect transistors 有权
    散射场效应晶体管的制造方法

    公开(公告)号：US07176067B2

    公开(公告)日：2007-02-13

    申请号：US10869763

    申请日：2004-06-16

    Applicant: In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    Inventor： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC: H01L21/339

    CPC classification number: H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers
    40.
    发明授权
    Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers 有权
    制造具有保护层的Fin场效应晶体管（Fin-FET）的方法

    公开(公告)号：US07141456B2

    公开(公告)日：2006-11-28

    申请号：US10871742

    申请日：2004-06-18

    Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    IPC: H01L21/84 ,  H01L21/332

    CPC classification number: H01L29/7851 ,  H01L29/66795

    Abstract: Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

    Abstract translation: 提供制造鳍场效应晶体管（Fin-FET）的方法。 翅片形成在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层形成在沟槽中，使得第一绝缘层的表面在鳍片的暴露在翅片的侧壁的表面下方凹进。 保护层形成在第一绝缘层上，并且第二绝缘层形成在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。 还提供了相关的Fin-FET。

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