Plate-type heat exchanger and fuel cell system with the same
    31.
    发明申请
    Plate-type heat exchanger and fuel cell system with the same 失效
    板式换热器和燃料电池系统相同

    公开(公告)号:US20070160885A1

    公开(公告)日:2007-07-12

    申请号:US11650415

    申请日:2007-01-08

    IPC分类号: H01M8/04 H01M8/06

    摘要: A plate-type heat exchanger for use in a fuel cell system that has a fuel cell stack and a reformer is provided. The heat exchanger includes a substrate and a pair of cover plates. The substrate has a first face and a second face opposite to the first face. The substrate is disposed between the cover plates, and combined with the cover plates to form a first passageway and a second passageway. The first passageway is formed in the first face and circulates steam discharged from the fuel cell stack. The steam or water condensed from the steam is supplied to a water supply source. The second passageway is formed in the second face, and circulates water supplied from the water supply source. The water is supplied to the reformer after the circulation. The heat exchanger of the present invention improves performance and efficiency of a fuel cell system.

    摘要翻译: 提供一种用于具有燃料电池堆和重整器的燃料电池系统中的板式热交换器。 热交换器包括基板和一对盖板。 基板具有与第一面相对的第一面和第二面。 基板设置在盖板之间,并与盖板组合以形成第一通道和第二通道。 第一通道形成在第一面中并使从燃料电池堆排出的蒸汽循环。 从蒸汽冷凝的蒸汽或水被供应到供水源。 第二通道形成在第二面中,并且循环从供水源供应的水。 水循环后供应给重整器。 本发明的热交换器提高燃料电池系统的性能和效率。

    Arbitration circuit to arbitrate conflict between read/write command and scan command and display driver integrated circuit having the same
    32.
    发明授权
    Arbitration circuit to arbitrate conflict between read/write command and scan command and display driver integrated circuit having the same 有权
    仲裁电路来仲裁读/写命令和扫描命令之间的冲突以及具有相同的显示驱动器集成电路

    公开(公告)号:US08711162B2

    公开(公告)日:2014-04-29

    申请号:US12686508

    申请日:2010-01-13

    IPC分类号: G09G5/39 G06F15/167

    CPC分类号: G09G5/001 G09G3/20 G09G5/39

    摘要: An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation.

    摘要翻译: 仲裁电路,用于仲裁读/写命令和扫描命令之间的问题以及包括仲裁电路的显示驱动器集成电路。 仲裁电路包括一个锁存单元,该锁存单元具有锁存和输出与扫描命令有关的第一信号的第一锁存电路和锁存并输出与读/写命令相关的第二信号的第二锁存电路,其中锁存单元复位输出 的第一锁存电路和/或第二锁存电路响应于与存储器操作相关的就绪信号,以及维持单元,用于接收第一锁存电路和第二锁存电路的输出,以产生第一内部信号以激活 扫描操作和第二内部信号以激活读/写操作,保持第一内部信号和第二内部信号,并且通过改变第一内部信号或第二内部信号中的至少一个的状态来选择性地启动第一内部信号或第二内部信号 第一内部信号和第二内部信号响应复位操作。

    NEGATIVE VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE
    33.
    发明申请
    NEGATIVE VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE 有权
    负电压发生器和半导体存储器件

    公开(公告)号:US20120206988A1

    公开(公告)日:2012-08-16

    申请号:US13358121

    申请日:2012-01-25

    IPC分类号: G11C7/12 G11C7/00

    CPC分类号: G11C11/419 G11C5/145 G11C7/12

    摘要: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

    摘要翻译: 负电压发生器包括可变电容负电压产生单元,开关单元和正电压施加单元。 负电压产生单元包括用于改变负电压被充电的电容的多个耦合电容器。 负电压产生单元根据写入数据的存储体组的行数(大小)选择多个耦合电容器中的至少一个耦合电容器,并将至少一个所选择的耦合电容器充电至负电压。 切换单元响应于数据选择具有互补的第一和第二位线的位线对的一个位线,并且将至少一个选择的耦合电容器连接到所选择的位线。 正电压施加单元将正(高)电压施加到位线对的另一位线。

    ZOOM LENS BARREL ASSEMBLY
    34.
    发明申请
    ZOOM LENS BARREL ASSEMBLY 有权
    变焦镜头棒组件

    公开(公告)号:US20120206820A1

    公开(公告)日:2012-08-16

    申请号:US13280575

    申请日:2011-10-25

    IPC分类号: G02B7/04

    摘要: A zoom lens barrel assembly including: a first zoom ring comprising a first protrusion; a guide ring disposed around the first zoom ring comprising a first guide slot through which the first protrusion passes, and a second guide slot; a second zoom ring comprising a second protrusion, and movable in an axial direction; a first cylinder comprising a guide groove into which the second protrusion inserts, and a third protrusion passing through the second guide slot, and disposed between the first and second zoom rings; a second cylinder disposed around the guide ring comprising a fourth protrusion, a first groove portion into which the first protrusion inserts, and a second groove portion into which the third protrusion inserts, and supporting the first zoom ring and the first cylinder; and an external cylinder disposed around the second cylinder and comprising a third groove portion into which the fourth protrusion inserts.

    摘要翻译: 一种变焦镜头组件,包括:第一变焦环,包括第一突起; 设置在所述第一变焦环周围的引导环,包括所述第一突起穿过的第一引导槽和第二引导槽; 第二变焦环,包括第二突起,并且可沿轴向移动; 第一气缸,包括第二突起插入的引导槽和穿过第二引导槽的第三突起,并且设置在第一和第二变焦环之间; 设置在所述导向环周围的第二圆筒,包括第四突起,所述第一突起插入其中的第一凹槽部分和所述第三突起插入并支撑所述第一变焦环和所述第一气缸的第二凹槽部分; 以及设置在所述第二圆筒周围并包括第三凹槽部分的外圆筒,所述第四凸起插入所述第三凹槽部分。

    Reaction vessel and reaction device
    39.
    发明授权
    Reaction vessel and reaction device 有权
    反应容器和反应装置

    公开(公告)号:US07842260B2

    公开(公告)日:2010-11-30

    申请号:US11877562

    申请日:2007-10-23

    IPC分类号: B01J8/02 C01B3/02

    摘要: Provided is a reaction vessel for a fuel cell, and more particularly to a reaction vessel exhibiting improved thermal efficiency, and a reaction device for a steam reforming reaction for a fuel cell. The reaction device includes a cylindrical reaction catalyst chamber on which a target reaction catalyst for a predetermined target reaction is disposed; and a tubular oxidation catalyst chamber surrounding the reaction catalyst chamber, comprising an oxidation reaction catalyst therein. The reaction device according features an increased contact area between catalyst and gas, and rapidly heating of the gas in contact with the catalyst to a desired reaction temperature.

    摘要翻译: 提供一种用于燃料电池的反应容器,更具体地说,涉及一种表现出改善的热效率的反应容器,以及用于燃料电池的蒸汽重整反应的反应装置。 反应装置包括:圆筒状的反应催化剂室,配置有用于规定的目标反应的目标反应催化剂; 以及围绕反应催化剂室的管状氧化催化剂室,其中包含氧化反应催化剂。 反应装置的特征在于催化剂和气体之间的接触面积增加,并且将与催化剂接触的气体快速加热到所需的反应温度。

    Write driver circuit of an unmuxed bit line scheme
    40.
    发明授权
    Write driver circuit of an unmuxed bit line scheme 有权
    写未驱动位线方案的驱动电路

    公开(公告)号:US07821845B2

    公开(公告)日:2010-10-26

    申请号:US12184321

    申请日:2008-08-01

    IPC分类号: G11C7/10

    摘要: A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver.

    摘要翻译: 一种半导体存储器的写入驱动器电路,用于提供一种未复位的位线方案,其减小了未变形的Y路径的高度,以便减小存储器中芯片的面积。 写入驱动器电路可以包括输入锁存电路,其响应于输入使能信号锁存输入数据; 第一写驱动器,响应于写使能信号接收从输入锁存电路输出的写数据,并将数据输出到位线; 以及第二写入驱动器,其响应于所述写入使能信号接收从所述输入锁存电路输出的写入数据的反向数据,并将数据输出到互补位线,其中所述第一和第二写入驱动器具有与非门类型结构 并用作写入驱动器和预充电驱动器。