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    Write driver circuit of an unmuxed bit line scheme
    1.
    发明授权
    Write driver circuit of an unmuxed bit line scheme 有权
    写未驱动位线方案的驱动电路

    公开(公告)号：US07821845B2

    公开(公告)日：2010-10-26

    申请号：US12184321

    申请日：2008-08-01

    申请人： Jong-hoon Jung ,  Chan-ho Lee

    发明人： Jong-hoon Jung ,  Chan-ho Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1048 ,  G11C7/1096 ,  G11C7/12

    摘要： A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver.

    摘要翻译： 一种半导体存储器的写入驱动器电路，用于提供一种未复位的位线方案，其减小了未变形的Y路径的高度，以便减小存储器中芯片的面积。 写入驱动器电路可以包括输入锁存电路，其响应于输入使能信号锁存输入数据; 第一写驱动器，响应于写使能信号接收从输入锁存电路输出的写数据，并将数据输出到位线; 以及第二写入驱动器，其响应于所述写入使能信号接收从所述输入锁存电路输出的写入数据的反向数据，并将数据输出到互补位线，其中所述第一和第二写入驱动器具有与非门类型结构 并用作写入驱动器和预充电驱动器。

    3D display panel and 3D display apparatus using the same and driving method thereof
    2.
    发明授权
    3D display panel and 3D display apparatus using the same and driving method thereof 有权
    3D显示面板和使用其的3D显示装置及其驱动方法

    公开(公告)号：US09325980B2

    公开(公告)日：2016-04-26

    申请号：US13267502

    申请日：2011-10-06

    申请人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

    发明人： Jong-hoon Jung ,  Dae-sik Kim ,  Kyung-hoon Cha ,  Ho-seop Lee ,  Young-ji Ko

    IPC分类号： G09G3/36 ,  H04N13/04

    CPC分类号： H04N13/341 ,  H04N13/398

    摘要： A three-dimensional (3D) display panel, a 3D display apparatus using the same, and a driving method thereof are provided. The 3D display apparatus includes: an image display panel which displays an image; a phase shift panel which alternately shifts a polarization direction of light outputted from the image display panel; a backlight unit which provides a backlight; and a control unit which turns off the backlight unit during a crosstalk period where the phase shift panel performs the shift operation and to turn on the backlight unit for a stabilization period after the crosstalk period.

    摘要翻译： 提供三维（3D）显示面板，使用其的3D显示装置及其驱动方法。 3D显示装置包括：显示图像的图像显示面板; 相移面板，其交替地偏移从所述图像显示面板输出的光的偏振方向; 提供背光的背光单元; 以及控制单元，其在相移面板执行移位操作的串扰时段期间关闭背光单元，并且在串扰周期之后的稳定时段接通背光单元。

    Backlight unit for liquid crystal display device
    3.
    发明授权
    Backlight unit for liquid crystal display device 有权
    背光单元用于液晶显示装置

    公开(公告)号：US08360591B2

    公开(公告)日：2013-01-29

    申请号：US12478023

    申请日：2009-06-04

    申请人： Jong-hoon Jung

    发明人： Jong-hoon Jung

    IPC分类号： G09F13/04 ,  G09F13/08

    CPC分类号： G02F1/133603 ,  G02F1/133608 ,  G02F2001/133612

    摘要： Provided is a backlight unit for a liquid crystal display device. The backlight unit includes: a chassis; a printed circuit board connected to a side of the chassis, the printed circuit board including a plurality of light emitting diodes, and a pair of conductive pads through which power is supplied to the light emitting diodes, wherein the pair of conductive pads are disposed on an end of the printed circuit board; and a power socket into which the pair of the conductive pads are inserted.

    摘要翻译： 提供了一种用于液晶显示装置的背光单元。 背光单元包括：底盘; 连接到底盘一侧的印刷电路板，印刷电路板包括多个发光二极管，以及一对导电焊盘，通过该导电焊盘向发光二极管供电，其中一对导电焊盘设置在 印刷电路板的一端; 以及插入一对导电垫的电源插座。

    Semiconductor memory device for reducing precharge time
    4.
    发明申请
    Semiconductor memory device for reducing precharge time 有权
    用于减少预充电时间的半导体存储器件

    公开(公告)号：US20080310243A1

    公开(公告)日：2008-12-18

    申请号：US12155885

    申请日：2008-06-11

    申请人： Jong-hoon Jung ,  Gyu-hong Kim

    发明人： Jong-hoon Jung ,  Gyu-hong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12

    摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

    摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

    Semiconductor integrated circuit, method of designing the same, and method of fabricating the same
    5.
    发明授权
    Semiconductor integrated circuit, method of designing the same, and method of fabricating the same 有权
    半导体集成电路及其设计方法及其制造方法

    公开(公告)号：US09026975B2

    公开(公告)日：2015-05-05

    申请号：US13800483

    申请日：2013-03-13

    申请人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

    发明人： Tae-joong Song ,  Pil-un Ko ,  Gyu-hong Kim ,  Jong-hoon Jung

    IPC分类号： G06F17/50 ,  H01L27/092 ,  H01L27/02

    CPC分类号： G06F17/5072 ,  G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/6681

    摘要： A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

    摘要翻译： 提供了一种半导体集成电路设计方法及其制造方法，该方法能够最小化由导线，特别是栅极线，半导体集成电路中的开销产生的寄生电容及其制造方法。 一种设计具有FinFET架构的半导体集成电路的方法，包括：对要设计的半导体集成电路进行预仿真; 基于预仿真的结果设计半导体集成电路的部件的布局，所述部件包括第一和第二器件区域以及跨越第一和第二器件区域延伸的第一导电线; 根据至少一个设计规则修改布置在第一和第二设备区域之间并且电切割第一导电线的第一切割区域，以使由第一切割区域产生的第一导电线路的开销最小化。

    Semiconductor memory device for reducing precharge time
    9.
    发明授权
    Semiconductor memory device for reducing precharge time 有权
    用于减少预充电时间的半导体存储器件

    公开(公告)号：US07852694B2

    公开(公告)日：2010-12-14

    申请号：US12155885

    申请日：2008-06-11

    申请人： Jong-hoon Jung ,  Gyu-hong Kim

    发明人： Jong-hoon Jung ,  Gyu-hong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12

    摘要： A semiconductor memory device for reducing a precharge time is provided. The semiconductor memory device may include a sense amplifier, a precharge unit and an equalizing circuit. The sense amplifier may sense and amplify a difference between data transmitted through a first bit line and data transmitted through a second bit line in response to a sense amplifier enable signal. The precharge unit may precharge voltage levels of the first bit line and the second bit line to a precharge voltage level in response to a precharge enable signal. The equalizing circuit may be connected to the sense amplifier and the precharge unit and may control the voltage levels of the first bit line and the second bit line to be equal to each other in response to the sense amplifier enable signal. The semiconductor memory device may reduce a time required to perform a precharge operation and/or minimize an increase of the circuit size.

    摘要翻译： 提供一种用于减少预充电时间的半导体存储器件。 半导体存储器件可以包括读出放大器，预充电单元和均衡电路。 感测放大器可以响应于读出放大器使能信号来感测和放大通过第一位线传输的数据与通过第二位线传输的数据之间的差异。 预充电单元可以响应于预充电使能信号而将第一位线和第二位线的电压电压预充电到预充电电压电平。 均衡电路可以连接到读出放大器和预充电单元，并且可以响应于读出放大器使能信号而将第一位线和第二位线的电压电平控制为彼此相等。 半导体存储器件可以减少执行预充电操作所需的时间和/或最小化电路尺寸的增加。

    Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data
    10.
    发明申请
    Semiconductor memory devices for outputting bit cell data without separate reference voltage generator and related methods of outputting bit cell data 有权
    用于输出位单元数据而不用单独的参考电压发生器的半导体存储器件以及输出位单元数据的相关方法

    公开(公告)号：US20050018470A1

    公开(公告)日：2005-01-27

    申请号：US10864276

    申请日：2004-06-09

    申请人： Jong-hoon Jung

    发明人： Jong-hoon Jung

    IPC分类号： G11C11/4096 ,  G11C7/06 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/24

    CPC分类号： G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4099

    摘要： Semiconductor memory devices are provided which include an array of memory cells, an array of reference cells, and a plurality of sense amplifiers that are associated with respective of the memory cells. The reference cells have a first capacitor that is coupled to a first supply voltage, to a first complementary bit line associated with one of the memory cells and to a second complementary bit line that is associated with a different memory cell. The sense amplifiers are configured to sense and amplify the voltage difference between a signal on the first bit line and a signal on the first complementary bit line. These semiconductor memory devices may output bit cell data without a separate reference voltage generator.

    摘要翻译： 提供了半导体存储器件，其包括存储器单元阵列，参考单元阵列以及与相应存储器单元相关联的多个读出放大器。 参考单元具有耦合到第一电源电压的第一电容器，与与存储器单元之一相关联的第一互补位线和与不同存储器单元相关联的第二互补位线。 读出放大器被配置为感测和放大第一位线上的信号与第一互补位线上的信号之间的电压差。 这些半导体存储器件可以输出比特单元数据，而不需要单独的参考电压发生器。