公开(公告)号：US20090165718A1

公开(公告)日：2009-07-02

申请号：US12344489

申请日：2008-12-27

Applicant: Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

Inventor： Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

IPC: C23C16/00

CPC classification number: C23C14/12 ,  C23C14/243 ,  C23C14/246 ,  C23C14/26

Abstract: Provided are a gas injector and a film deposition apparatus having the same. The gas injector includes a body, a supply hole, an injection hole, and a distribution plate. The body is configured to provide an inner space therein. The supply hole is formed in an upper surface of the body to communicate with the inner space and receive a raw material. The injection hole is formed in a lower surface of the body to communicate with the inner space and inject the raw material. The distribution plate is disposed in the inner space of the body. A through hole is formed in the distribution plate. The distribution plate is disposed to be inclined at a predetermined angle with respect to a horizontal plane. The gas injector can uniformly inject the raw material and improve vaporization efficiency of the raw material having a powder form.

Abstract translation: 提供了一种气体注入器和具有该气体注入器的成膜装置。 气体喷射器包括主体，供给孔，喷射孔和分配板。 身体构造成在其中提供内部空间。 供应孔形成在主体的上表面中以与内部空间连通并且接收原料。 注入孔形成在主体的下表面中，与内部空间连通并注入原料。 分配板设置在主体的内部空间中。 在分配板上形成通孔。 分配板相对于水平面倾斜预定角度。 气体喷射器可以均匀地注入原料并提高具有粉末形式的原料的蒸发效率。

公开(公告)号：US06593631B2

公开(公告)日：2003-07-15

申请号：US09850004

申请日：2001-05-08

Applicant: Chang-Jae Lee ,  Jong-Kwan Kim

Inventor： Chang-Jae Lee ,  Jong-Kwan Kim

IPC: H01L2976

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process. Also, by providing a conductive layer between the first and second gates, which electrically connects those gates, mutual diffusion of the impurities doping the polysilicon layers is prevented.

Abstract translation: 制造半导体器件的方法包括以下步骤：在衬底中形成第一导电类型和第二导电类型的阱; 在衬底上形成场氧化物层和栅极氧化物层; 在所述场氧化物层和栅极氧化物层上形成第一和第二多晶硅层，所述第一多晶硅层掺杂有第二导电类型的杂质，所述第二多晶硅层掺杂有第一导电性的杂质，所述第一和第二多晶硅层接触 彼此; 将第一和第二多晶硅层图形化以彼此隔离，从而形成第一和第二栅极; 以及在所述第一和第二栅极之间形成导电层。 因此，为了形成栅极的目的，使用一个掩模来进行N型和P型多晶硅层的隔离以及它们的图案化，有效地简化了栅极图案化工艺期间的蚀刻工艺。 此外，通过在第一和第二栅极之间提供导电层，其电连接这些栅极，防止掺杂多晶硅层的杂质的相互扩散。

公开(公告)号：US06080615A

公开(公告)日：2000-06-27

申请号：US2679

申请日：1998-01-05

Applicant: Chang-Jae Lee ,  Jun-Ki Kim

Inventor： Chang-Jae Lee ,  Jun-Ki Kim

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/105 ,  H01L21/8242

CPC classification number: H01L28/40 ,  H01L27/0629

Abstract: A method for fabricating an integrated circuit includes the steps of forming an isolating insulation film on a portion of a semiconductor substrate, forming a gate insulating film, a first conductive layer, an insulating film and a second conductive layer successively on the semiconductor substrate including the isolating insulation film, selectively removing the second conductive layer and the insulating film to pattern an upper electrode of a capacitor in a capacitor forming region and a dummy gate electrode in a transistor forming region, respectively, forming a lower electrode mask in the capacitor forming region, and selectively removing the first conductive layer and the gate insulating film by using the lower electrode mask and the dummy gate electrode as masks, to form a lower electrode of the capacitor and the gate electrode of the transistor.

Abstract translation: 一种用于制造集成电路的方法包括以下步骤：在半导体衬底的一部分上形成隔离绝缘膜，在半导体衬底上依次形成栅绝缘膜，第一导电层，绝缘膜和第二导电层， 隔离绝缘膜，选择性地去除第二导电层和绝缘膜，以分别在晶体管形成区域中的电容器形成区域中的电容器的上电极和伪栅极电极，以在电容器形成区域中形成下电极掩模 并且通过使用下电极掩模和伪栅极作为掩模来选择性地去除第一导电层和栅极绝缘膜，以形成电容器的下电极和晶体管的栅电极。

公开(公告)号：US6057232A

公开(公告)日：2000-05-02

申请号：US862926

申请日：1997-05-27

Applicant: Chang-Jae Lee

Inventor： Chang-Jae Lee

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L23/53223 ,  H01L23/485 ,  H01L2924/0002

Abstract: A metal wiring for semiconductor devices having a double-layer passivation film structure consisting of an intermetallic compound layer formed on a copper thin film and made of a metal reacting with copper to form an intermetallic compound and a metal nitride layer formed over the intermetallic compound. This double-layer passivation film structure is obtained by depositing a metal layer, capable of reacting with copper to form an intermetallic compound, over the copper wiring, and annealing the metal layer in a nitrogen atmosphere, thereby forming an intermetallic compound layer over the copper wiring. By virtue of the double-layer passivation film structure, the copper wiring has a great improvement in the reliability. A metal silicide layer is formed between a diffusion region and a diffusion barrier layer in the contact hole of the semiconductor device. The diffusion barrier layer, which is formed on an insulating layer doped with nitrogen ions, is changed into a metal nitride film. Accordingly, a reduced ohmic contact resistance and an improved passivation reliability are achieved.

Abstract translation: 一种用于半导体器件的金属布线，具有双层钝化膜结构，该双层钝化膜结构由在铜薄膜上形成的金属间化合物层组成，并由金属与铜反应形成金属间化合物，金属氮化物层形成在金属间化合物上。 通过在铜布上沉积能够与铜反应以形成金属间化合物的金属层，并在氮气气氛中退火金属层，从而在铜上形成金属间化合物层，从而获得双层钝化膜结构 接线。 由于双层钝化膜结构，铜布线的可靠性有很大的提高。 在半导体器件的接触孔中的扩散区域和扩散阻挡层之间形成金属硅化物层。 在掺有氮离子的绝缘层上形成的扩散阻挡层变成金属氮化物膜。 因此，实现了降低的欧姆接触电阻和改善的钝化可靠性。

公开(公告)号：US5646052A

公开(公告)日：1997-07-08

申请号：US633002

申请日：1996-04-16

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L21/76202 ,  H01L21/76235 ,  H01L21/763

Abstract: A method of forming a semiconductor device by concurrently forming both single-trenched small field regions and double-trench-extension large field regions, and the device so formed. The method includes: forming an insulating layer on a substrate; forming a mask layer on the insulating layer to cover only active regions such that small field regions and large field regions are left uncovered by the mask layer; increasing a thickness of the insulating layer in each field region in proportion to the width of that field region; removing all of the insulating layer in the small field regions while removing only some of the insulating layer in the large field regions so that, in width cross-section, the large field regions have an exposed substrate narrow edge-area that borders both sides of a remaining portion of the insulating layer; forming trenches in the substrate corresponding in location to the exposed substrate areas such that an intermediate-width trench is created in each small field region and such that a wide trench, having two trench-deepening extensions, is created in each large field region; putting conductive material into the trenches such that the trench-deepening extensions are filled completely and the intermediate-width trenches are at least partially filled; and converting a portion of the conductive material into an insulating cap.

Abstract translation: 通过同时形成单沟槽小场区域和双沟槽扩展大场区域形成半导体器件的方法以及如此形成的器件。 该方法包括：在基板上形成绝缘层; 在绝缘层上形成掩模层以仅覆盖有源区域，使得小场区域和大场区域被掩模层覆盖; 在每个场区域中增加与该场区域的宽度成比例的绝缘层的厚度; 去除小场区域中的所有绝缘层，同时仅去除大场区域中的一些绝缘层，使得在宽截面中，大场区域具有暴露的基板窄边缘区域 绝缘层的剩余部分; 在衬底中形成相应于暴露的衬底区域的衬底中的沟槽，使得在每个小场区域中形成中间宽度沟槽，并且使得在每个大场区域中形成具有两个沟槽深化延伸部的宽沟槽; 将导电材料放入沟槽中，使得沟槽加深延伸部完全填充并且中间宽度沟槽至少部分地被填充; 以及将导电材料的一部分转换成绝缘帽。

公开(公告)号：US5567244A

公开(公告)日：1996-10-22

申请号：US172463

申请日：1993-12-23

Applicant: Chang-Jae Lee ,  Hyeung-Tae Kim

Inventor： Chang-Jae Lee ,  Hyeung-Tae Kim

IPC: H01L21/304 ,  C01G3/04 ,  H01L21/302 ,  H01L21/306 ,  B08B3/08

CPC classification number: H01L21/02052 ,  C01G3/04 ,  Y10S134/902

Abstract: The present invention provides a process for cleaning semiconductor devices which enables the contamination of copper to maintained under a level of about 10.sup.9 atoms/cm.sup.2 to meet the qualification of DRAMs of equal to or greater than 64M bits in capacity by means of supplying O.sub.3 to a solution, resulting in great reproducibility and reliability. According to the present invention, a mechanism for removing a copper impurity in a semiconductor device uses oxygen to form a cupric oxide, which forms a cupric fluoride, which is then removed from the solution.

Abstract translation: 本发明提供一种用于清洁半导体器件的方法，其能够将铜的污染保持在约109原子/ cm 2的水平，以通过向O3提供等于或大于64M位的DRAM的资格来满足 解决方案，具有很好的重现性和可靠性。 根据本发明，用于去除半导体器件中的铜杂质的机构使用氧来形成氧化铜，其形成氟化铜，然后从溶液中除去。

公开(公告)号：US5201991A

公开(公告)日：1993-04-13

申请号：US659004

申请日：1991-02-21

Applicant: Chang-Jae Lee

Inventor： Chang-Jae Lee

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L28/40

Abstract: A process for formation of a multi-stack type capacitor is disclosed, which comprises: steps of forming a polysilicon layer 5 on a source, forming a dielectric 5a, forming a layer 6, and forming a dielectric layer 6a in the cited order; step of self-aligning a contact pattern for connecting the layer 5 and the layer 7; step of carrying out an etching so as for the layer 5 and the layer 7 to be connected later; steps of forming the layer 7, and forming a dielectric layer 7a; step of self-aligning a contact pattern for connecting the layer 6 and a layer 8; step of carrying out an etching so as for the layer 6 and the layer 8 to be connected later; and step of forming the layer 8, the above steps being repeated in order to form a multi-stack type capacitor of a sandwiched form. According to the present invention, the device is protected from the etch damage, and is suitable for use in a high density memory device.

Abstract translation: 公开了一种用于形成多堆叠型电容器的工艺，其包括：在源极上形成多晶硅层5的步骤，形成电介质5a，形成层6，并按照所述顺序形成电介质层6a; 自对准用于连接层5和层7的接触图案的步骤; 进行蚀刻以使层5和层7稍后连接的步骤; 形成层7的步骤，形成电介质层7a; 自对准用于连接层6和层8的接触图案的步骤; 进行蚀刻的步骤，以使层6和层8稍后连接; 以及形成层8的步骤，重复上述步骤以形成夹层形式的多层叠型电容器。 根据本发明，保护器件免受蚀刻损伤，适用于高密度存储器件。

公开(公告)号：US08628621B2

公开(公告)日：2014-01-14

申请号：US12344489

申请日：2008-12-27

Applicant: Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

Inventor： Hyung Sup Lee ,  Sung Tae Nam Goong ,  Kyoo Hwan Lee ,  Young Ho Kwon ,  Chang Jae Lee

IPC: C23C16/00 ,  B05B1/24 ,  B05B1/00

CPC classification number: C23C14/12 ,  C23C14/243 ,  C23C14/246 ,  C23C14/26

Abstract: Provided are a gas injector and a film deposition apparatus having the same. The gas injector includes a body, a supply hole, an injection hole, and a distribution plate. The body is configured to provide an inner space therein. The supply hole is formed in an upper surface of the body to communicate with the inner space and receive a raw material. The injection hole is formed in a lower surface of the body to communicate with the inner space and inject the raw material. The distribution plate is disposed in the inner space of the body. A through hole is formed in the distribution plate. The distribution plate is disposed to be inclined at a predetermined angle with respect to a horizontal plane. The gas injector can uniformly inject the raw material and improve vaporization efficiency of the raw material having a powder form.

Abstract translation: 提供了一种气体注入器和具有该气体注入器的成膜装置。 气体喷射器包括主体，供给孔，喷射孔和分配板。 身体构造成在其中提供内部空间。 供应孔形成在主体的上表面中以与内部空间连通并且接收原料。 注入孔形成在主体的下表面中，与内部空间连通并注入原料。 分配板设置在主体的内部空间中。 在分配板上形成通孔。 分配板相对于水平面倾斜预定角度。 气体喷射器可以均匀地注入原料并提高具有粉末形式的原料的蒸发效率。

公开(公告)号：US20120309927A1

公开(公告)日：2012-12-06

申请号：US13324127

申请日：2011-12-13

Applicant: Yong Tae KIM ,  Jin Kyu KIM ,  Bok Nam JANG ,  Joong In KIM ,  Young Jun KIM ,  Ji Heung KIM ,  Chang Jae LEE

Inventor： Yong Tae KIM ,  Jin Kyu KIM ,  Bok Nam JANG ,  Joong In KIM ,  Young Jun KIM ,  Ji Heung KIM ,  Chang Jae LEE

IPC: C08G65/38

CPC classification number: C08G65/44 ,  C08L71/12

Abstract: Polyarylene ether is polymerized using a dissolving agent including anisole, wherein the polyarylene ether includes about 1 to about 3,000 ppm of anisole.

Abstract translation: 使用包括苯甲醚的溶解剂聚合聚芳醚，其中聚亚芳基醚包括约1至约3,000ppm的苯甲醚。

公开(公告)号：US08317922B2

公开(公告)日：2012-11-27

申请号：US12344486

申请日：2008-12-27

Applicant: Chang Jae Lee ,  Young-Ho Kwon

Inventor： Chang Jae Lee ,  Young-Ho Kwon

IPC: C23C16/455 ,  C23C16/448 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

CPC classification number: C23C14/12 ,  C23C14/243 ,  C23C14/246 ,  C23C14/26 ,  F28F13/003

Abstract: A gas injection unit and a thin film deposition apparatus having the gas injection unit are provided. Since a variety of different kinds of organic materials can be sequentially vaporized and injected by a single injection unit, a variety of different kinds of thin films can be deposited in a single chamber. Furthermore, the gas injection structure of the injector unit can be easily controlled. Therefore, even when the process conditions such as the size of the substrate, the process temperature of the chamber, and the like are altered, it becomes possible to actively response to the altered process conditions by simply replacing some parts without replacing the whole injector unit.

Abstract translation: 提供了具有气体注入单元的气体注入单元和薄膜沉积设备。 由于可以通过单个注射单元顺序地蒸发和注入各种不同种类的有机材料，所以可以在单个室中沉积各种不同种类的薄膜。 此外，可以容易地控制喷射器单元的气体注入结构。 因此，即使在基板的尺寸，室的处理温度等的处理条件发生变化的情况下，也可以通过简单地更换一些部件而不更换整个喷射器单元来主动地响应于改变的工艺条件 。