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40 条记录 (耗时 0.018 秒)

    Device in a memory circuit for definition of waiting times
    31.
    发明授权
    Device in a memory circuit for definition of waiting times 有权
    用于定义等待时间的存储器电路中的器件

    公开(公告)号：US07355921B2

    公开(公告)日：2008-04-08

    申请号：US11386043

    申请日：2006-03-21

    申请人： Andre Schaefer ,  Thomas Hein ,  Christian Weis

    发明人： Andre Schaefer ,  Thomas Hein ,  Christian Weis

    IPC分类号： G11C8/00

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076

    摘要： A device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

    摘要翻译： 用于定义在特定操作开始之后通过时钟控制的存储器电路的等待时间的装置，直到可以开始后续操作。 该设备包括布置在存储器电路中的数字定时器，当特定操作开始时被接通，并且允许在经过限定的时间段之后开始后续操作。 数字定时器在其接通之后，计数从时钟信号导出的周期性计数脉冲，以便一旦计数了所需数量的这些脉冲，就发出等待时间结束的信号。 提供等待时间调整装置，并且可以通过存储器电路的外部连接来访问，以便设置所需数量的计数脉冲。

    Method and circuit arrangement for controlling write access to a semiconductor memory
    32.
    发明授权
    Method and circuit arrangement for controlling write access to a semiconductor memory 有权
    用于控制对半导体存储器的写访问的方法和电路装置

    公开(公告)号：US07224625B2

    公开(公告)日：2007-05-29

    申请号：US11117698

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

    摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

    摘要翻译： 本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动， 要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存 ，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。 本发明还涉及一种用于执行该方法的电路装置。

    Device in a memory circuit for definition of waiting times
    33.
    发明申请
    Device in a memory circuit for definition of waiting times 有权
    用于定义等待时间的存储器电路中的器件

    公开(公告)号：US20060233005A1

    公开(公告)日：2006-10-19

    申请号：US11386043

    申请日：2006-03-21

    申请人： Andre Schaefer ,  Thomas Hein ,  Christian Weis

    发明人： Andre Schaefer ,  Thomas Hein ,  Christian Weis

    IPC分类号： G11C19/08

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076

    摘要： The invention relates to a device for definition of the waiting time which should pass in a clock-controlled memory circuit after the start of a specific operation until a subsequent operation may be started. The device includes a digital timer which is arranged in the memory circuit, is switched on when the specific operation is initiated and allows the subsequent operation to be started after a defined time period has elapsed. The digital timer, after it is switched on, counts periodic counting pulses which are derived from the clock signal, in order to signal the end of the waiting time as soon as it has counted a desired number of these pulses. A waiting time adjustment apparatus is provided and is accessible via external connections of the memory circuit in order to set the desired number of counting pulses.

    摘要翻译： 本发明涉及一种用于定义等待时间的装置，该等待时间应在特定操作开始之后通过时钟控制的存储器电路，直到可以开始后续操作。 该设备包括布置在存储器电路中的数字定时器，当特定操作开始时被接通，并且允许在经过限定的时间段之后开始后续操作。 数字定时器在其接通之后，计数从时钟信号导出的周期性计数脉冲，以便一旦计数了所需数量的这些脉冲，就发出等待时间结束的信号。 提供等待时间调整装置，并且可以通过存储器电路的外部连接来访问，以便设置所需数量的计数脉冲。

    Method and circuit arrangement for controlling write access to a semiconductor memory
    34.
    发明申请
    Method and circuit arrangement for controlling write access to a semiconductor memory 有权
    用于控制对半导体存储器的写访问的方法和电路装置

    公开(公告)号：US20050254307A1

    公开(公告)日：2005-11-17

    申请号：US11117698

    申请日：2005-04-29

    申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

    CPC分类号： G11C7/22 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/229

    摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

    摘要翻译： 本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动， 要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存 ，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。 本发明还涉及一种用于执行该方法的电路装置。

    Integrated memory, and a method of operating an integrated memory
    35.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Bearing module for an actuating element
    38.
    发明授权
    Bearing module for an actuating element 失效
    用于致动元件的轴承模块

    公开(公告)号：US06279883B1

    公开(公告)日：2001-08-28

    申请号：US09416791

    申请日：1999-10-13

    申请人： Christian Weis

    发明人： Christian Weis

    IPC分类号： B60G1102

    CPC分类号： B60K26/021 ,  G05G1/44 ,  G05G5/03 ,  Y10T74/20534 ,  Y10T74/20888

    摘要： The bearing module (10) is used to support an actuating element which can be displaced counter to the force of at least one return spring (32) with a force hysteresis due to friction. With previous bearing modules, complex friction mechanisms which ensure the desired hysteresis are provided in addition to the return springs. To reduce the number of parts necessary for a bearing module, the proposal is that the force should be transmitted from the return spring (32) via a friction element (24) which slides on a friction surface (28) assigned to the return spring (32) during the displacement, either tensioning the spring (32) or being returned by it. The direct production of hysteresis in the return mechanism reduces the number of components and hence the costs of production for the bearing module (10).

    摘要翻译： 轴承模块（10）用于支撑致动元件，其可以由于摩擦而具有与至少一个复位弹簧（32）的力相反的力滞后的位移。 对于先前的轴承模块，除了复位弹簧之外，还提供了确保所需滞后的复杂摩擦机构。 为了减少轴承模块所需的部件数量，建议力应通过在分配给复位弹簧的摩擦表面（28）上滑动的摩擦元件（24）从复位弹簧（32）传递 32），张紧弹簧（32）或由其返回。 在返回机构中直接产生滞后减少了部件的数量，并因此减少了轴承模块（10）的生产成本。

    Synchronous integrated memory
    39.
    发明授权
    Synchronous integrated memory 有权
    同步集成存储器

    公开(公告)号：US06275445B1

    公开(公告)日：2001-08-14

    申请号：US09617649

    申请日：2000-07-17

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Torsten Partsch ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1078

    摘要： A memory has data lines through which data connections are connected to groups of memory cells via a synchronizing unit. The synchronizing unit is disposed adjacent to the cell group and has a clock input to which an internal clock signal is fed. In the event of a write access to the memory, the synchronizing unit synchronizes with the internal clock signal data signals that are fed via the data connections and are synchronous with an external clock signal.

    摘要翻译： 存储器具有数据线，数据连接经由同步单元连接到存储器单元组。 同步单元被布置成与单元组相邻并且具有被馈送内部时钟信号的时钟输入。 在对存储器进行写访问的情况下，同步单元与经由数据连接馈送的内部时钟信号数据信号同步，并与外部时钟信号同步。