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    Integrated memory, and a method of operating an integrated memory
    2.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Circuit configuration with a memory array
    6.
    发明授权
    Circuit configuration with a memory array 有权

    公开(公告)号：US06614700B2

    公开(公告)日：2003-09-02

    申请号：US10116826

    申请日：2002-04-05

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22

    摘要： The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

    Integrated memory
    8.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06437410B1

    公开(公告)日：2002-08-20

    申请号：US09603749

    申请日：2000-06-26

    申请人： Stefan Dietrich ,  Musa Saglam ,  Peter Schrögmeier ,  Michael Markert ,  Sabine Schöniger ,  Christian Weis

    发明人： Stefan Dietrich ,  Musa Saglam ,  Peter Schrögmeier ,  Michael Markert ,  Sabine Schöniger ,  Christian Weis

    IPC分类号： H01L2976

    CPC分类号： G11C7/1066 ,  G11C8/00 ,  G11C8/10

    摘要： The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

    摘要翻译： 集成存储器具有第一地址路径，通过该第一地址路径，地址端子连接到第一组的第一选择线并且具有对应的第一行和第一解码器电路。 此外，集成存储器具有第二地址路径，通过该第二地址路径，地址端子连接到第二组的第一选择线并具有对应的第二线和第二解码器电路。 第一解码器电路比第二解码器电路快。 第一行具有比第二行更长的信号传播时间。

    Control circuit for an S-DRAM
    9.
    发明授权
    Control circuit for an S-DRAM 有权
    用于S-DRAM的控制电路

    公开(公告)号：US06717886B2

    公开(公告)日：2004-04-06

    申请号：US10248874

    申请日：2003-02-26

    申请人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    发明人： Acharya Pramod ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/4076

    摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

    摘要翻译： 用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟 具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。

    Method and circuit configuration for read-write mode control of a synchronous memory
    10.
    发明授权
    Method and circuit configuration for read-write mode control of a synchronous memory 有权
    用于同步存储器的读写模式控制的方法和电路配置

    公开(公告)号：US06359832B2

    公开(公告)日：2002-03-19

    申请号：US09773222

    申请日：2001-01-31

    申请人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/12 ,  G11C11/4094

    摘要： A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.

    摘要翻译： 描述了一种读写模式控制方法，其中可以通过在第一电路部分中进行具有自动预充电的读取指令来缩短读取处理期间的等待时间。 第一电路部分与用于执行写指令的第二电路部分分开，因为存储器控制器不需要在写指令和相关联的激活信号之间插入任何等待周期。