公开(公告)号：US20070238273A1

公开(公告)日：2007-10-11

申请号：US11394614

申请日：2006-03-31

Applicant: Brian Doyle ,  Suman Datta ,  Jack Kavalieros ,  Amlan Majumdar

Inventor： Brian Doyle ,  Suman Datta ,  Jack Kavalieros ,  Amlan Majumdar

IPC: H01L21/425

CPC classification number: H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.

Abstract translation: 描述了用于三栅极场效应晶体管的用于离子注入尖端源极和漏极区域和晕圈区域的方法。 在一个实施例中，从六个不同的角度植入硅体，以获得理想的区域。

公开(公告)号：US20070231984A1

公开(公告)日：2007-10-04

申请号：US11395940

申请日：2006-03-31

Applicant: Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Robert Chau

IPC: H01L21/8234

CPC classification number: H01L21/8234 ,  H01L21/28518 ,  H01L21/28562 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.

Abstract translation: 对三维晶体管的制造方法进行说明。 原子层在一个实施方案中，镍的沉积用于在所有外延生长的源极和漏极区域上形成均匀的硅化物，包括面向下的源极和漏极区域。

公开(公告)号：US07176090B2

公开(公告)日：2007-02-13

申请号：US10936114

申请日：2004-09-07

Applicant: Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Suman Datta ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L21/82385 ,  H01L21/28114 ,  H01L21/30608 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/66545 ,  Y10S438/926

Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成在第一层上并且比第一层更宽。 在除去牺牲结构以产生沟槽之后，在沟槽内形成金属栅电极。

公开(公告)号：US20070029627A1

公开(公告)日：2007-02-08

申请号：US11545313

申请日：2006-10-10

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Justin Brask ,  Robert Chau

IPC: H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract translation: 在金属栅极更换工艺中，杯状栅极金属氧化物电介质可以具有可暴露于硅离子注入的垂直部分。 作为注入的结果，可以减小垂直部分的介电常数，减少边缘电容。

公开(公告)号：US07170120B2

公开(公告)日：2007-01-30

申请号：US11096984

申请日：2005-03-31

Applicant: Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

Inventor： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L29/76

CPC classification number: H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

公开(公告)号：US20060281236A1

公开(公告)日：2006-12-14

申请号：US11508009

申请日：2006-08-21

Applicant: Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

Inventor： Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

IPC: H01L21/84

CPC classification number: G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

Abstract translation: 本发明是包括两个存取装置的CMOS SRAM单元，每个存取装置由具有单个鳍片的三栅晶体管组成; 两个上拉装置，每个上拉装置由具有单个鳍片的三栅极晶体管组成; 和两个下拉器件，每个下拉器件由具有多个鳍片的三栅晶体管组成。 还提供了一种用于制造包括双鳍三栅极晶体管的CMOS SRAM单元的方法。

公开(公告)号：US07126199B2

公开(公告)日：2006-10-24

申请号：US10951073

申请日：2004-09-27

Applicant: Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Chris Barns ,  Matthew V. Metz ,  Suman Datta ,  Robert S. Chau

IPC: H01L29/94

CPC classification number: H01L21/823437 ,  H01L21/823828

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

Abstract translation: 互补金属氧化物半导体集成电路可以形成有在半导体衬底上具有高介电常数栅极电介质材料的NMOS和PMOS晶体管。 可以在栅极电介质上方形成金属阻挡层。 在金属阻挡层上方形成功函设定金属层，在功函设定金属层上形成帽金属层。

公开(公告)号：US20060220090A1

公开(公告)日：2006-10-05

申请号：US11089247

申请日：2005-03-23

Applicant: Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Marko Radosavljevic ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Mark Doczy ,  Jack Kavalieros ,  Justin Brask ,  Brian Doyle ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L29/516 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.

Abstract translation: 描述半导体器件。 该半导体器件包括形成在位于衬底内的沟道上的高k栅介质层和形成在高k栅介质层上的金属栅电极。 高k栅极电介质层具有优于基于二氧化硅的栅极电介质的截止状态泄漏特性，以及优于包含各向同性材料的高k栅极电介质的导通状态迁移率特性。

公开(公告)号：US20060214237A1

公开(公告)日：2006-09-28

申请号：US11418577

申请日：2006-05-05

Applicant: Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

Inventor： Matthew Metz ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC: H01L29/94 ,  H01L29/76

CPC classification number: H01L21/823828 ,  H01L21/823857

Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

公开(公告)号：US20060183277A1

公开(公告)日：2006-08-17

申请号：US10742678

申请日：2003-12-19

Applicant: Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Chris Barns ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

Inventor： Justin Brask ,  Mark Doczy ,  Jack Kavalieros ,  Uday Shah ,  Matthew Metz ,  Chris Barns ,  Suman Datta ,  Christopher Thomas ,  Robert Chau

IPC: H01L21/8234 ,  H01L21/31

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/31691 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层上形成牺牲层。 在蚀刻牺牲层之后，在牺牲层的相对侧上形成第一和第二间隔物。 在去除牺牲层以产生位于第一和第二间隔物之间​​的沟槽之后，在高k栅介质层上形成金属层。