公开(公告)号：US20060274583A1

公开(公告)日：2006-12-07

申请号：US11144264

申请日：2005-06-03

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

公开(公告)号：US20050157549A1

公开(公告)日：2005-07-21

申请号：US10762181

申请日：2004-01-21

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。

公开(公告)号：US20050003616A1

公开(公告)日：2005-01-06

申请号：US10600259

申请日：2003-06-20

申请人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

发明人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

摘要翻译： 公开了浮动栅极结构，其具有远离衬底的表面延伸的突起。 该突起可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

公开(公告)号：US5627097A

公开(公告)日：1997-05-06

申请号：US498709

申请日：1995-07-03

申请人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze

发明人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/70

CPC分类号： H01L29/66575 ,  H01L21/823814

摘要： A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

摘要翻译： 具有减小的寄生结电容的CMOS器件和用于制造器件的工艺。 该器件包括从形成在半导体衬底（12）中的掩埋层（16,18）垂直分离源区和漏区（52和53,54和55）的未掺杂外延层（20）的一部分（20'）。 未掺杂的外延层（20）通过提供本征硅区域来物理地分离来自源极和漏极区域的高掺杂剂浓度的区域，从而减小了源极和漏极区域的结电容。 另外，根据本发明制造的MOS晶体管具有从未掺杂的外延层（20）的上表面（22）延伸到位于半导体衬底（12）中的掩埋层（16,18）的完全自对准沟道区， 。

公开(公告)号：US07961511B2

公开(公告)日：2011-06-14

申请号：US11535452

申请日：2006-09-26

申请人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

发明人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.

摘要翻译： 描述了将非易失性存储器单元编程到最终编程状态的混合方法。 所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。 混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程 单元格到最终编程状态。 另外，所描述的方法对于编程多级芯片是特别有利的。

公开(公告)号：US07630254B2

公开(公告)日：2009-12-08

申请号：US12018279

申请日：2008-01-23

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

公开(公告)号：US07457178B2

公开(公告)日：2008-11-25

申请号：US11331479

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C29/00

CPC分类号： G11C16/30 ,  G11C11/5628 ,  G11C16/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US07447086B2

公开(公告)日：2008-11-04

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20080116502A1

公开(公告)日：2008-05-22

申请号：US12024808

申请日：2008-02-01

申请人： Jeffrey Lutze ,  Nima Mokhlesi

发明人： Jeffrey Lutze ,  Nima Mokhlesi

IPC分类号： H01L29/788

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

摘要： A memory system is disclosed that includes a set of non-volatile storage elements. Each of the non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

摘要翻译： 公开了一种包括一组非易失性存储元件的存储器系统。 每个非易失性存储元件包括在衬底中的沟道的相对侧处的源极/漏极区域以及在沟道上方的浮动栅极堆叠。 存储器系统还包括位于相邻浮动栅极堆叠之间并电连接到源极/漏极区域的一组屏蔽板，用于减少相邻浮动栅极之间的耦合。 屏蔽板选择性地生长在存储器的有效区域上，而不会在非活动区域上生长。 在一个实施例中，屏蔽板是位于源/漏区上方的外延生长的硅。

公开(公告)号：US07349258B2

公开(公告)日：2008-03-25

申请号：US11295776

申请日：2005-12-06

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.