公开(公告)号：US08097304B2

公开(公告)日：2012-01-17

申请号：US11567926

申请日：2006-12-07

Applicant: Hyuk-soon Choi ,  Hyo-sug Lee ,  June-mo Koo ,  Kwang-hee Kim

Inventor： Hyuk-soon Choi ,  Hyo-sug Lee ,  June-mo Koo ,  Kwang-hee Kim

IPC: B05D5/00

CPC classification number: B05D3/0263 ,  B05D1/00 ,  B05D1/185 ,  B05D2401/32 ,  B22F1/0018 ,  B22F1/0062 ,  B22F2998/00 ,  B82Y10/00 ,  B82Y30/00 ,  Y10T428/24355 ,  Y10T428/24372 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/2462 ,  B22F1/0022

Abstract: A method of forming a nano-particle array by convective assembly and a convective assembly apparatus for the same are provided. The method of forming nano-particle array comprises: coating a plurality of nano-particles by forming a coating layer; performing a first convective assembly by moving a first substrate facing, in parallel to and spaced apart from a second substrate at a desired distance such that a colloidal solution including the coated nano-particles is between the first and second substrate; and performing a second convective assembly for evaporating a solvent by locally heating a surface of the colloidal solution drawn when the first substrate is moved in parallel relative to the second substrate. The present invention provides the method of forming the nano-particle array where nano-particles having a particle size from a few to several tens of nanometers are uniformly arrayed on a large area substrate at a low cost, and the convective assembly apparatus for the same.

Abstract translation: 提供了通过对流组装形成纳米颗粒阵列的方法和用于其的对流组装装置。 形成纳米颗粒阵列的方法包括：通过形成涂层来涂覆多个纳米颗粒; 通过将第一衬底移动到与第二衬底平行并间隔开所需距离的方式执行第一对流组件，使得包含涂覆的纳米颗粒的胶体溶液位于第一和第二衬底之间; 以及执行用于蒸发溶剂的第二对流组件，其通过局部加热当所述第一衬底相对于所述第二衬底平行移动时所绘制的所述胶体溶液的表面而蒸发溶剂。 本发明提供了形成纳米粒子阵列的方法，其中纳米粒子具有几个到几十个纳米的粒子以低成本均匀地排列在大面积基底上，而对流装配装置 。

公开(公告)号：US08014068B2

公开(公告)日：2011-09-06

申请号：US11760812

申请日：2007-06-11

Applicant: Byoung-ho Cheong ,  Jae-young Choi ,  June-mo Koo ,  Moon-gyu Lee

Inventor： Byoung-ho Cheong ,  Jae-young Choi ,  June-mo Koo ,  Moon-gyu Lee

IPC: G02B5/30

CPC classification number: G02B5/3058 ,  Y10S359/90

Abstract: A wire grid polarizer and a method of manufacturing the wire grid polarizer are provided. The wire grid polarizer includes: a substrate; and a plurality of core-shell nano wires arranged on the substrate and including wire cores and polymer shells enclosing the wire cores to a predetermined thickness.

Abstract translation: 提供了线栅偏振器和制造线栅偏振器的方法。 线栅偏振器包括：基板; 以及多个芯 - 壳纳米线，其布置在所述基板上并且包括将所述线芯围绕预定厚度的线芯和聚合物壳。

公开(公告)号：US07948024B2

公开(公告)日：2011-05-24

申请号：US12484339

申请日：2009-06-15

Applicant: Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

Inventor： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

Abstract: A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

Abstract translation: 提供了一种非易失性存储装置，包括： 沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层， 所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层 栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。

公开(公告)号：US07932551B2

公开(公告)日：2011-04-26

申请号：US11902511

申请日：2007-09-21

Applicant: Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

Inventor： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66803

Abstract: A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.

Abstract translation: 提供非易失性存储器件。 在非易失性存储器件中，第一导电类型的半导体衬底包括第一和第二鳍片。 公共位线电极将第一鳍片的一端连接到第二鳍片的一端。 控制栅电极覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。 位于公共位线电极和控制栅电极之间的第一串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。 位于第一串选择栅极电极和控制栅电极之间的第二串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。

公开(公告)号：US07894265B2

公开(公告)日：2011-02-22

申请号：US12081679

申请日：2008-04-18

Applicant: Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

Inventor： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

Abstract: The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.

Abstract translation: 非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。 编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

公开(公告)号：US07885115B2

公开(公告)日：2011-02-08

申请号：US12318651

申请日：2009-01-05

Applicant: Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

Inventor： Tae-hee Lee ,  Won-joo Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.

Abstract translation: 提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。 从多个位线确定用于编程的选择位线和用于防止编程的未选位线。 对从多个字线中选择的至少一个禁止字线施加抑制电压。 至少一个禁止字线包括最靠近字符串选择线定位的字线。 将编程电压施加到从多个字线中选择的选定字线。 数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

公开(公告)号：US07829932B2

公开(公告)日：2010-11-09

申请号：US11980632

申请日：2007-10-31

Applicant: Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

Inventor： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

IPC: H01L29/788

CPC classification number: H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

Abstract: Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

Abstract translation: 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对使用（或功能）作为活性区的翅片。 半导体柱可以插入翅片的部分之间以连接散热片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

公开(公告)号：US07750393B2

公开(公告)日：2010-07-06

申请号：US11987008

申请日：2007-11-26

Applicant: Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

Inventor： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7885 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.

Abstract translation: 提供了非易失性存储器件的示例性实施例及其制造方法。 非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层， 插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。 第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。 换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

公开(公告)号：US20100072452A1

公开(公告)日：2010-03-25

申请号：US12585582

申请日：2009-09-18

Applicant: Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

Inventor： Suk-pil Kim ,  June-mo Koo ,  Tae-eung Yoon

IPC: H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Provided is a non-volatile memory device having a stacked structure that is easily highly integrated and a method of economically fabricating the non-volatile memory device. The non-volatile memory device may include at least one first electrode and at least one second electrode that cross each other. At least one data storage layer may be disposed on a section where the at least one first electrode and the at least one second electrode cross each other. The at least one first electrode may include a first conductive layer and a first semiconductor layer.

Abstract translation: 提供了具有容易高度集成的堆叠结构的非易失性存储器件以及经济地制造非易失性存储器件的方法。 非易失性存储器件可以包括至少一个第一电极和至少一个彼此交叉的第二电极。 至少一个数据存储层可以设置在至少一个第一电极和至少一个第二电极彼此交叉的部分上。 所述至少一个第一电极可以包括第一导电层和第一半导体层。

公开(公告)号：US20090122613A1

公开(公告)日：2009-05-14

申请号：US12149213

申请日：2008-04-29

Applicant: Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

Inventor： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon ,  Tae-hee Lee

IPC: G11C16/06 ,  G11C11/34

CPC classification number: G11C16/10 ,  G11C2213/71

Abstract: A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.

Abstract translation: 非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。 多个NAND串可以在多个半导体层上。 多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。 公共位线可以在存储器单元的第一端处共同连接到每个NAND串。 公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。 多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。