公开(公告)号：US20070002620A1

公开(公告)日：2007-01-04

申请号：US11170950

申请日：2005-06-30

Applicant: Richard Fastow ,  Krishna Parat ,  Johnny Javanifard

Inventor： Richard Fastow ,  Krishna Parat ,  Johnny Javanifard

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

Abstract translation: 存储器阵列包括耦合的控制器，用于控制对存储器单元的存储器单元和存储器单元的块的写入，读取和擦除。 控制器在擦除过程中可操作以确定和减少奇数/偶数字线偏移。 控制器可以单独设置的奇/偶字线擦除电压进行操作，这些电压被调整以影响偏移。

公开(公告)号：US06949801B2

公开(公告)日：2005-09-27

申请号：US10669825

申请日：2003-09-23

Applicant: Krishna Parat ,  Kiran Pangal ,  Allen Lu

Inventor： Krishna Parat ,  Kiran Pangal ,  Allen Lu

IPC: H01L21/762 ,  H01L29/76

CPC classification number: H01L21/76229

Abstract: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.

Abstract translation: 一种用于在衬底中形成浅和深隔离沟槽的方法和装置，使得浅和深隔离沟槽被对准而不被错配。 该方法包括形成多个浅沟槽，覆盖多个浅沟槽的一部分，然后蚀刻未覆盖的浅沟槽以产生更深的沟槽。

公开(公告)号：US06849518B2

公开(公告)日：2005-02-01

申请号：US10141545

申请日：2002-05-07

Applicant: Krishna Parat ,  Kiran Pangal ,  Allen Lu

Inventor： Krishna Parat ,  Kiran Pangal ,  Allen Lu

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76229

Abstract: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.

公开(公告)号：US06265292B1

公开(公告)日：2001-07-24

申请号：US09351498

申请日：1999-07-12

Applicant: Krishna Parat ,  Raghupathy V. Giridhar ,  Cheng C. Hu ,  Daniel Xu ,  Yudong Kim ,  Glen Wada

Inventor： Krishna Parat ,  Raghupathy V. Giridhar ,  Cheng C. Hu ,  Daniel Xu ,  Yudong Kim ,  Glen Wada

IPC: H01L21425

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11536

Abstract: A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.

Abstract translation: 描述了制造闪速存储器集成电路的方法。 在本发明的一个实施例中，在硅衬底中形成介质填充沟槽隔离区。 电介质填充沟槽隔离区域将硅衬底的第一部分与硅衬底的第二部分隔离。 然后去除沟槽中的电介质的一部分，以在硅衬底的第一和第二部分之间的沟槽中露出硅衬底的一部分。 然后植入离子以在硅衬底的第一部分中形成第一源极区域，并在硅衬底的第二部分中形成第二源极区域，并且在沟槽中的透明硅衬底中形成掺杂区域，其中掺杂 沟槽中的区域从第一掺杂源区延伸到第二掺杂源区。

公开(公告)号：US5835328A

公开(公告)日：1998-11-10

申请号：US914290

申请日：1997-08-18

Applicant: Timothy J. Maloney ,  Krishna Parat

Inventor： Timothy J. Maloney ,  Krishna Parat

IPC: H02H9/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. Generally, the arrangement provides protection against voltage transients for certain circumstances and disables such protection for other circumstances. Transient protection is enabled when the power of the transient would cause breakdown of the transistors of the integrated circuit. Otherwise, transient protection is disabled.

Abstract translation: 用于防止由于在集成电路外部引入的电压瞬变而导致对集成电路的电路的损坏的装置。 通常，该装置在某些情况下提供了针对电压瞬变的保护，并且在其他情况下禁止这种保护。 当瞬态功率将导致集成电路晶体管的击穿时，瞬态保护被使能。 否则，暂时保护被禁用。

公开(公告)号：US09251907B2

公开(公告)日：2016-02-02

申请号：US13438331

申请日：2012-04-03

Applicant: Akira Goda ,  Yijie Zhao ,  Krishna Parat

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.

Abstract translation: 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。

公开(公告)号：US09135998B2

公开(公告)日：2015-09-15

申请号：US12942152

申请日：2010-11-09

Applicant: Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F12/00 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

公开(公告)号：US07582530B2

公开(公告)日：2009-09-01

申请号：US11478776

申请日：2006-06-30

Applicant: Henry Chao ,  Krishna Parat

Inventor： Henry Chao ,  Krishna Parat

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Formation techniques are utilized to increase the space or distance between floating gates of a memory array of floating gate transistors. In at least some embodiments, floating gates are first formed over the substrate and then portions of the floating gates are removed to increase the spacing between the floating gates. An interlayer dielectric layer is then formed over the substrate and a control gate layer is formed thereover.

Abstract translation: 利用形成技术来增加浮动栅极晶体管的存储器阵列的浮置栅极之间的空间或距离。 在至少一些实施例中，首先在衬底上形成浮动栅极，然后去除浮动栅极的部分以增加浮动栅极之间的间隔。 然后在衬底上形成层间电介质层，并在其上形成控制栅极层。

公开(公告)号：US20080001208A1

公开(公告)日：2008-01-03

申请号：US11478776

申请日：2006-06-30

Applicant: Henry Chao ,  Krishna Parat

Inventor： Henry Chao ,  Krishna Parat

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Formation techniques are utilized to increase the space or distance between floating gates of a memory array of floating gate transistors. In at least some embodiments, floating gates are first formed over the substrate and then portions of the floating gates are removed to increase the spacing between the floating gates. An interlayer dielectric layer is then formed over the substrate and a control gate layer is formed thereover.

Abstract translation: 利用形成技术来增加浮动栅极晶体管的存储器阵列的浮置栅极之间的空间或距离。 在至少一些实施例中，首先在衬底上形成浮动栅极，然后去除浮动栅极的部分以增加浮动栅极之间的间隔。 然后在衬底上形成层间电介质层，并在其上形成控制栅极层。

公开(公告)号：US20070114592A1

公开(公告)日：2007-05-24

申请号：US11284485

申请日：2005-11-21

Applicant: Steven Soss ,  Krishna Parat

Inventor： Steven Soss ,  Krishna Parat

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of forming a microelectronic non-volatile memory cell, a non-volatile memory cell made according to the method, and a system comprising the non-volatile memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation regions in the substrate, providing the pair comprising providing a buffer layer on the substrate; removing the buffer layer; providing a tunnel dielectric on a surface of the substrate after removing the buffer layer; providing a pair of device spacers on side walls of each of the isolation regions extending above the surface of the substrate; providing a floating gate on the tunnel dielectric; providing a source region and a drain region on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.

Abstract translation: 一种形成微电子非易失性存储单元的方法，根据该方法制造的非易失性存储单元，以及包括非易失性存储单元的系统。 该方法包括：提供衬底; 在衬底中提供一对间隔开的隔离区域，提供该对包括在衬底上提供缓冲层; 去除缓冲层; 在去除所述缓冲层之后，在所述衬底的表面上提供隧道电介质; 在衬底的表面上方延伸的每个隔离区的侧壁上设置一对器件间隔物; 在隧道电介质上提供浮动栅极; 在所述浮动栅极的相对侧上设置源极区域和漏极区域; 在所述浮动栅极上提供互补电介质; 以及在所述互聚电介质上提供控制栅极以产生所述存储单元。