公开(公告)号：US6002114A

公开(公告)日：1999-12-14

申请号：US153044

申请日：1998-09-15

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: F24H9/20 ,  G05D23/19 ,  H05B1/02

CPC classification number: G05D23/1931 ,  F24H9/2028

Abstract: A control device installed in an electric water heater to control its operation, the control device including a water temperature control circuit and a power control circuit, the water temperature control circuit being formed of a water temperature detection circuit, which detects water temperature at the water inlet and the water outlet of the electric water heater, a water flow rate detection circuit, which detects the flow rate of water passing through the water inlet, a CPU, an indicator circuit controlled by the CPU to indicate the working conditions of the electric water heater, and a digital display controlled by the CPU to show the value of water temperature at the water outlet, the power control circuit being formed of a power supply circuit, a TRAIC triggering control circuit, which turns on the heating elements of the electric water heater alternatively subject AC phase change, a TRAIC power circuit, which provides the TRAIC triggering control circuit with the base power, an AC phase detection input circuit, a relay circuit controlled by the CPU to cut off power supply from the electric water heater when an abnormal condition occurs, a failure detection circuit, which outputs a signal to the CPU when an abnormal condition of the electric water heater is detected, causing the CPU to cut off power supply from the electric water heater, and an overheat protection circuit for overheat protection.

Abstract translation: 一种安装在电热水器中以控制其操作的控制装置，所述控制装置包括水温控制电路和功率控制电路，所述水温控制电路由水温检测电路形成，所述水温检测电路检测所述水的水温 电热水器的入口和出水口，检测通过入水口的水的流量的水流量检测电路，CPU，由CPU控制的指示电路，以指示电水的工作条件 加热器和由CPU控制的数字显示器，以显示出水口的水温值，功率控制电路由电源电路，TRAIC触发控制电路构成，TRAIC触发控制电路接通电水的加热元件 加热器交替相位变化，TRAIC电源电路，为TRAIC触发控制电路提供基本功率，a 交流相位检测输入电路，由CPU控制的继电器电路，当异常状态发生时切断电热水器的电源;故障检测电路，当电热水器的异常情况发生时，向CPU输出信号 被检测到，导致CPU切断来自电热水器的电源，以及用于过热保护的过热保护电路。

公开(公告)号：US09019771B2

公开(公告)日：2015-04-28

申请号：US13661723

申请日：2012-10-26

Applicant: Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

Inventor： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/0475 ,  G11C16/10

Abstract: A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

Abstract translation: 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US09000412B2

公开(公告)日：2015-04-07

申请号：US13561558

申请日：2012-07-30

Applicant: Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

Inventor： Wei-Chih Chien ,  Feng-Ming Lee ,  Ming-Hsiu Lee

IPC: H01L29/06 ,  G11C13/00 ,  H01L43/02 ,  H01L45/00

CPC classification number: G11C13/0002 ,  G11C13/003 ,  H01L27/2409 ,  H01L43/02 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract translation: 提供了一种切换装置及其操作方法及其存储器阵列。 开关装置包括第一固体电解质，第二固体电解质和开关层。 开关层与第一固体电解质和第二固体电解质相邻。

公开(公告)号：US08937291B2

公开(公告)日：2015-01-20

申请号：US13528754

申请日：2012-06-20

Applicant: Ming-Hsiu Lee ,  Wei-Chih Chien

Inventor： Ming-Hsiu Lee ,  Wei-Chih Chien

IPC: H01L47/00 ,  H01L29/06

CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/1022

Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

Abstract translation: 所公开的存储器件包括三维阵列结构，其包括设置在存储层之间的存储层和晶体管结构。 每个存储器层连接到公共电极，并且每个晶体管结构包括共享公共列结构和公共基极结构的晶体管。 晶体管还各自包括通过公共基底结构与公共柱结构间隔开的连接器结构。

公开(公告)号：US08824188B2

公开(公告)日：2014-09-02

申请号：US13567750

申请日：2012-08-06

Applicant: Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

Inventor： Feng-Min Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/77

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract translation: 提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。 存储器件的操作方法包括以下步骤。 使存储器件处于置位状态。 用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。 读取设置状态的存储器件。 一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。 将恢复的偏置电压施加到存储器件。 在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

公开(公告)号：US08809829B2

公开(公告)日：2014-08-19

申请号：US12484955

申请日：2009-06-15

Applicant: Ming-Hsiu Lee

Inventor： Ming-Hsiu Lee

IPC: H01L47/00

CPC classification number: H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.

Abstract translation: 具有在有源区域中具有改变的化学计量的相变材料元件的存储器件在设定状态电阻中不会出现漂移。 一种用于制造存储器件的方法包括：首先制造集成电路，该集成电路包括具有大体积化学计量的相变材料体的相变存储器单元的阵列; 然后将成形电流施加到阵列中的相变存储器单元，以将相变材料的主体的有源区域中的主体化学计量改变为改变的化学计量，而不会干扰有源区域外的主体化学计量。 主要化学计量学的特征在于在活性区域外的热力学条件下的稳定性，而改性的化学计量学的特征在于活性区域内的热力学条件下的稳定性。

公开(公告)号：US08743599B2

公开(公告)日：2014-06-03

申请号：US13421718

申请日：2012-03-15

Applicant: Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

Inventor： Matthew J. BrightSky ,  Roger W. Cheek ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0033 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641 ,  H01L45/1675

Abstract: A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

Abstract translation: 存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。 一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。 该方法包括改变相变材料的第一有界区域的开关体积的化学成分。 该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如 第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。 第一保留性与第二保留性不同。

公开(公告)号：US20140119127A1

公开(公告)日：2014-05-01

申请号：US13661723

申请日：2012-10-26

Applicant: Hsiang-Lan Lung ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING-HSIU LEE

Inventor： Hsiang-Lan Lung ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING-HSIU LEE

IPC: G11C16/06

CPC classification number: G11C16/0475 ,  G11C16/10

Abstract: A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

Abstract translation: 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US08634235B2

公开(公告)日：2014-01-21

申请号：US12823508

申请日：2010-06-25

Applicant: Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

Inventor： Hsiang-Lan Lung ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

Abstract translation: 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

公开(公告)号：US20130341753A1

公开(公告)日：2013-12-26

申请号：US13528754

申请日：2012-06-20

Applicant: Ming-Hsiu LEE ,  Wei-Chih CHIEN

Inventor： Ming-Hsiu LEE ,  Wei-Chih CHIEN

IPC: H01L27/102

CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/1022

Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.