公开(公告)号：US20100054031A1

公开(公告)日：2010-03-04

申请号：US12548241

申请日：2009-08-26

Applicant: Guido De Sandre ,  Marco Pasotti

Inventor： Guido De Sandre ,  Marco Pasotti

IPC: G11C11/00 ,  G11C8/10 ,  G11C7/00

CPC classification number: G11C13/0026 ,  G11C13/0004

Abstract: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

Abstract translation: 列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。 列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。 在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径， 在位线和编程阶段之间。

公开(公告)号：US07508716B2

公开(公告)日：2009-03-24

申请号：US10777457

申请日：2004-02-12

Applicant: Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

Inventor： Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14

Abstract: A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load.

Abstract translation: 用于非易失性存储单元的读出放大器包括参考单元，连接到参考单元的第一负载和可连接到非易失性存储单元的第二负载，第一负载和第二负载均具有可控电阻; 所述第一负载和所述第二负载的控制电路以与所述第一负载的第一导通端子和所述第二导通端子之间的工作电压无关的方式向所述第一负载和所述第二负载提供控制电压。

公开(公告)号：US07360068B2

公开(公告)日：2008-04-15

申请号：US10768401

申请日：2004-01-30

Applicant: Michele Borgatti ,  Lorenzo Cali' ,  Francesco Lertora ,  Marco Pasotti ,  Pier Luigi Rolandi

Inventor： Michele Borgatti ,  Lorenzo Cali' ,  Francesco Lertora ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC: G06F13/00

CPC classification number: G06F15/7867 ,  G11C16/30 ,  Y02D10/12 ,  Y02D10/13

Abstract: A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.

Abstract translation: 动态可重构处理单元包括微处理器和用于代码，数据和比特流的非易失性存储的嵌入式闪存。 嵌入式闪存包括现场可编程门阵列（FPGA）端口。 可重构处理单元还包括直接存储器访问（DMA）通道和用于FPGA重新配置的S-RAM嵌入式FPGA。 S-RAM嵌入式FPGA具有通过DMA通道连接到闪存的FPGA端口的FPGA编程接口。 微处理器，嵌入式闪存，DMA通道和S-RAM嵌入式FPGA集成为单芯片。

公开(公告)号：US06655758B2

公开(公告)日：2003-12-02

申请号：US10035909

申请日：2001-12-19

Applicant: Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  PierLuigi Rolandi

Inventor： Marco Pasotti ,  Guido De Sandre ,  Giovanni Guaitini ,  David Iezzi ,  Marco Poles ,  PierLuigi Rolandi

IPC: G11C1604

CPC classification number: G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

公开(公告)号：US06622106B2

公开(公告)日：2003-09-16

申请号：US09833754

申请日：2001-04-11

Applicant: Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

Inventor： Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC: H03B500

CPC classification number: G01R31/2824

Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

Abstract translation: 一种用于测试和校准集成振荡器电路的振荡频率的数字装置，所述测试和校准装置具有至少第一和第二控制参数，所述至少第一和第二控制参数对应于为集成振荡器寻找的振荡频率的预定值范围的极限值 并且其包括用于比较已知持续时间的信号和来自集成振荡器电路的信号的比较电路; 连接到比较电路的电路，用于产生来自集成振荡电路的信号的校准值; 以及用于强制将来自集成振荡器电路的信号的最终校准值存储到集成振荡器电路的存储和控制部分的电路。

公开(公告)号：US06469934B2

公开(公告)日：2002-10-22

申请号：US09738253

申请日：2000-12-14

Applicant: Guido de Sandre ,  Marco Pasotti ,  Pier Luigi Rolandi

Inventor： Guido de Sandre ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC: G11C1604

CPC classification number: G11C16/3468

Abstract: The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.

Abstract translation: 优化的软编程方法用于由多个被分组成扇区的单元组成的存储器中。 属于单个扇区的单元具有连接到多个字线的栅极端子和连接到多个局部位线的漏极端子。 软编程方法包括在扇区中选择至少一个局部位线，同时选择同一扇区中的所有字线。 相应的栅极电压被施加到所有字线，而具有预定值的恒定漏极电压被施加到局部位线。

公开(公告)号：US06400607B1

公开(公告)日：2002-06-04

申请号：US09699304

申请日：2000-10-27

Applicant: Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi ,  Guido De Sandre

Inventor： Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi ,  Guido De Sandre

IPC: G11C1606

CPC classification number: G11C16/28 ,  G11C11/5642

Abstract: A reading circuit having an array branch connected to a multi-level array memory cell; a reference branch connected to a reference memory cell; a current/voltage converter stage formed of a current mirror having a variable mirror ratio, connected to the array and reference branches, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated respectively to the currents flowing in the array branch and in the reference branch; and a comparator stage having a first and a second input connected to the array and reference nodes for comparing with one another the array and reference potentials.

Abstract translation: 一种读取电路，具有连接到多级阵列存储单元的阵列分支; 连接到参考存储单元的参考分支; 电流/电压转换器级由具有可变镜像比的电流镜形成，连接到阵列和参考分支，并在阵列节点和参考节点分别提供阵列电位和参考电位，其分别与 在阵列分支和参考分支中流动的电流; 以及比较器级，其具有连接到阵列的第一和第二输入以及用于彼此比较阵列和参考电位的参考节点。

公开(公告)号：US06314043B1

公开(公告)日：2001-11-06

申请号：US09592796

申请日：2000-06-13

Applicant: Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G11C800

CPC classification number: G11C8/10 ,  G11C16/08

Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, including at least one row decoding circuit including at least two adder blocks, suitable to generate a row address signal, at least two decoder blocks, suitable to generate respective pluralities of signals identifying a respective sector of memory to be enabled, at least two shifter blocks, suitable to generate an address signal of another row to be enabled, at least two OR logic blocks, suitable to generate respective signals serving the purpose to simultaneously enable at least two rows of the memory matrix.

Abstract translation: 用于擦除和重写存储器单元，特别是模拟闪存单元的块的电路，包括至少一个行解码电路，其包括至少两个加法器块，所述至少两个加法器块适于生成行地址信号，至少两个解码器块，适于产生相应的多个 识别待启用的存储器的相应扇区的信号，至少两个移位器块，适于生成待使能的另一行的地址信号，至少两个OR逻辑块，适于产生用于至少同时使能的各个信号 两行内存矩阵。

公开(公告)号：US06232753B1

公开(公告)日：2001-05-15

申请号：US09467726

申请日：1999-12-20

Applicant: Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G05F1557

CPC classification number: G05F1/565

Abstract: A voltage regulator is provided for limiting overcurrents when used with a plurality of loads, particularly in flash memories, which are connected between an output node of the regulator and a voltage reference by way of a plurality of switches. The voltage regulator includes at least one differential stage that has a non-inverting input terminal for a control voltage, and an inverting input terminal connected to the voltage reference and the output node of the regulator through a feedback network. There is an output terminal connected to the output node of the voltage regulator to produce an output reference voltage from a comparison of input voltages. In the voltage regulator is a main control transistor connected between a high-voltage reference and the output terminal of the regulator. Advantageously, the regulator further includes a number of balance transistors connected between the high-voltage reference and the output node of the regulator and driven according to the load being connected to the output node, thereby to shorten the duration of an overcurrent at the output terminal while delivering the current required by the loads.

Abstract translation: 提供了一种电压调节器，用于在多个负载（特别是闪存）中使用时，限制过电流，其通过多个开关连接在调节器的输出节点和电压基准之间。 电压调节器包括至少一个差分级，其具有用于控制电压的非反相输入端，反相输入端通过反馈网连接到稳压器的电压基准和输出节点。 输出端连接到电压调节器的输出节点，以从输入电压的比较产生输出参考电压。 在电压调节器中是连接在高压基准和调节器的输出端之间的主控晶体管。 有利地，调节器还包括连接在调节器的高压基准和输出节点之间的多个平衡晶体管，其根据连接到输出节点的负载而驱动，从而缩短输出端子处的过电流的持续时间 同时提供负载所需的电流。

公开(公告)号：US06195289B1

公开(公告)日：2001-02-27

申请号：US09425446

申请日：1999-10-22

Applicant: Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G11C1606

CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C11/5642 ,  G11C27/005 ,  G11C27/02

Abstract: A read device comprises a sense amplifier having an input connected to a data memory cell to be read and an output issuing a signal correlated to the threshold voltage of the data memory cell. A first and second voltage sources circuit have respect first and second outputs that supply respective first and a second input reference voltage. A resistive divider connected between the first and the second outputs of the voltage source circuits has a plurality of outputs supplying respective intermediate reference voltages having values between the first and the second input reference voltages. A plurality of comparator circuits have a first input connected to the output of the sense amplifier, a second input connected to a respective output of the resistive divider, and an output supplying a digital signal indicative of the outcome of a respective comparison. Each voltage source circuit comprises a nonvolatile reference memory cell of the same type as the data memory cell and having an own threshold voltage correlated to the input reference voltage, supplied by the voltage source circuit. Thereby, the input reference voltages, and thus the intermediate reference voltages supplied to the comparator circuits, undergo variations in time correlated to the voltage supplied by the sense amplifier and consequent on the variations of the threshold voltages of the data memory cells.

Abstract translation: 读取装置包括具有连接到要读取的数据存储单元的输入的读出放大器和发出与数据存储单元的阈值电压相关的信号的输出。 第一和第二电压源电路涉及提供相应的第一和第二输入参考电压的第一和第二输出。 连接在电压源电路的第一和第二输出之间的电阻分压器具有多个输出，其提供具有在第一和第二输入参考电压之间的值的各个中间参考电压。 多个比较器电路具有连接到读出放大器的输出端的第一输入端，连接到电阻分压器的相应输出端的第二输入端，以及提供指示相应比较结果的数字信号的输出端。 每个电压源电路包括与数据存储单元相同类型的非易失性参考存储单元，并具有由电压源电路提供的与输入参考电压相关的自身阈值电压。 因此，输入参考电压以及因此提供给比较器电路的中间参考电压经历与由读出放大器提供的电压相关的时间变化，并且由此导致数据存储单元的阈值电压的变化。