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    Method And System For Establishing A System Time Within A Mobile Ad Hoc Network
    34.
    发明申请
    Method And System For Establishing A System Time Within A Mobile Ad Hoc Network 有权
    在移动Ad Hoc网络中建立系统时间的方法和系统

    公开(公告)号：US20090274137A1

    公开(公告)日：2009-11-05

    申请号：US12114312

    申请日：2008-05-02

    申请人： Mark D. Hall ,  Timothy M. Force

    发明人： Mark D. Hall ,  Timothy M. Force

    IPC分类号： H04J3/00

    CPC分类号： H04W56/001 ,  H04J3/0644

    摘要： A mobile ad hoc network, a mobile ad hoc network node and a method for establishing a system time within a mobile ad hoc network are provided. The network nodes may include a global positioning system (GPS) receiver for receiving GPS signals and for providing a GPS time derived from the GPS signals. The GPS time may be employed by the network node as the system time. Even though the network nodes of a mobile ad hoc network independently determine the GPS time and, in turn, the system time, the system time will be common for each of the network nodes. Mobile ad hoc network nodes may therefore join and leave the mobile ad hoc network with each network node being able to determine the system time prior to its joinder based upon the GPS time provided by the respective GPS receiver.

    摘要翻译： 提供了移动自组织网络，移动自组织网络节点和用于在移动自组织网络内建立系统时间的方法。 网络节点可以包括用于接收GPS信号并提供从GPS信号导出的GPS时间的全球定位系统（GPS）接收机。 GPS时间可以由网络节点用作系统时间。 即使移动自组织网络的网络节点独立地确定GPS时间，并且依次确定系统时间，系统时间对于每个网络节点将是共同的。 因此，移动自组织网络节点可以加入并离开移动自组织网络，每个网络节点能够根据由相应的GPS接收机提供的GPS时间来确定其加入之前的系统时间。

    Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration
    35.
    发明授权
    Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration 有权
    使用聚集的间隔凹槽蚀刻（ASRE）整合来改善具有间隔凹槽的自对准硅化物扩展性的方法

    公开(公告)号：US07563700B2

    公开(公告)日：2009-07-21

    申请号：US11360897

    申请日：2006-02-22

    申请人： Anadi Srivastava ,  Mark D. Hall ,  Raghaw S. Rai ,  Jesse Yanez

    发明人： Anadi Srivastava ,  Mark D. Hall ,  Raghaw S. Rai ,  Jesse Yanez

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/6656 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method is provided for making a silicided gate (209). In accordance with the method, a semiconductor structure (201) is provided which comprises a semiconductor substrate (202), a gate (209) disposed on the semiconductor substrate, and a spacer (219) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant (215) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide (225) is formed which extends over the first and second lateral portions of the gate.

    摘要翻译： 提供了一种制造硅化栅（209）的方法。 根据该方法，提供半导体结构（201），其包括半导体衬底（202），设置在半导体衬底上的栅极（209）和与栅极相邻的间隔物（219）。 对该结构进行暴露栅极的第一横向部分的第一蚀刻。 然后在与间隔物相邻的区域中产生植入物（215）。 然后对该结构进行暴露栅电极的第二横向部分的第二蚀刻，并且形成在栅极的第一和第二横向部分上延伸的硅化物层（225）。

    Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility
    36.
    发明授权
    Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility 失效
    未掺杂的栅极聚合，用于改进栅极图案化和硅化钴可扩展性

    公开(公告)号：US07491630B2

    公开(公告)日：2009-02-17

    申请号：US11375768

    申请日：2006-03-15

    申请人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

    发明人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

    IPC分类号： H01L21/04

    CPC分类号： H01L21/82345 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462

    摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

    摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。