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1.发明授权Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility 失效未掺杂的栅极聚合，用于改进栅极图案化和硅化钴可扩展性公开(公告)号：US07491630B2
公开(公告)日：2009-02-17
申请号：US11375768
申请日：2006-03-15
IPC分类号： H01L21/04
CPC分类号： H01L21/82345 , H01L21/823418 , H01L21/823456 , H01L21/823462
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.
摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。
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公开(公告)号：US20090142895A1
公开(公告)日：2009-06-04
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/8234
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US07745298B2
公开(公告)日：2010-06-29
申请号：US11948209
申请日：2007-11-30
IPC分类号： H01L21/336
CPC分类号： H01L21/823871 , H01L21/76897 , H01L21/823468 , H01L21/823475 , H01L29/665
摘要： A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
摘要翻译： 形成通孔的方法包括在半导体衬底上形成栅电极，在与栅电极相邻的半导体衬底中形成源极/漏极区域，在源/漏区域中形成硅化物区域，形成邻近硅化物间隔区 在形成硅化物区域之后形成栅电极，在栅电极，硅化物间隔物和硅化物区域之上形成层间电介质层，并且在层间电介质层中形成延伸到硅化物区域的导电通孔。
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公开(公告)号：US07911002B2
公开(公告)日：2011-03-22
申请号：US12641714
申请日：2009-12-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译： 提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113） 设置在所述介电层和所述第一和第二栅电极之间。
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5.发明授权Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer 有权通过选择性Ge缩合和高K电介质层选择性调制栅极功能的方法公开(公告)号：US07659156B2
公开(公告)日：2010-02-09
申请号：US11788216
申请日：2007-04-18
申请人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
发明人： Voon-Yew Thean , Marc Rossow , Gregory S. Spencer , Tab A. Stephens , Dina H. Triyoso , Victor H. Vartanian
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4908 , H01L29/513 , H01L29/517
摘要： A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.
摘要翻译： 提供一种半导体器件，其包括半导体层（109），介电层（111），具有与其相关联的第一和第二相应功函数的第一和第二栅电极（129,131）和氧化铪层（113） 设置在所述介电层和所述第一和第二栅电极之间。
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公开(公告)号：US20090294919A1
公开(公告)日：2009-12-03
申请号：US12130158
申请日：2008-05-30
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/02057 , H01L29/66795 , H01L29/66818
摘要： A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.
摘要翻译： 提供一种用于处理至少包括掩埋氧化物（BOX）层和半导体材料层的衬底的方法。 该方法包括蚀刻半导体材料层以形成覆盖BOX层的垂直半导体材料结构，留下BOX层的暴露部分。 该方法还包括将BOX层的暴露部分的顶表面暴露于抗氧化物蚀刻物质以形成覆盖BOX层的暴露部分的薄氧化物耐蚀刻层。
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7.发明申请ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN HAVING A PLURALITY OF GATE ELECTRODES AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权包括具有大量门电极的半导体器件的电子器件和用于形成电子器件的工艺公开(公告)号：US20080185654A1
公开(公告)日：2008-08-07
申请号：US11670833
申请日：2007-02-02
申请人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
发明人： Leo Mathew , Brian J. Goolsby , Tab A. Stephens
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.
摘要翻译： 电子设备可以包括具有与第一壁相邻的第一栅电极和与第二壁相邻的第二栅电极的半导体鳍。 在一个实施例中，可以形成覆盖半导体鳍片的导电构件，并且导电构件的一部分可以反应以形成第一和第二栅电极。 在另一个实施例中，可以形成图案化掩模层，其包括在栅极电极层上的掩模构件，并且可以去除覆盖在半导体鳍片上的掩蔽构件的部分。 在另一个实施例中，第一鳍式晶体管结构可以包括半导体鳍片，第一和第二栅电极以及第一绝缘帽。 电子器件还可以包括具有比第一绝缘盖更厚的第二绝缘帽的第二鳍式晶体管结构。
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公开(公告)号：US07208424B2
公开(公告)日：2007-04-24
申请号：US10943383
申请日：2004-09-17
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译： 在金属氧化物之上形成金属层，其中在半导体衬底上形成金属氧化物。 确定金属层的预定临界尺寸。 执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚。 用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。 在一个实施例中，在金属层上形成导电层。 可以蚀刻导电层的主体，留下与金属层接触的部分。 接下来，可以使用化学选择性地蚀刻与金属层接触的部分。
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9.发明申请公开(公告)号：US20140001641A1
公开(公告)日：2014-01-02
申请号：US13535028
申请日：2012-06-27
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L23/13 , H01L23/3157 , H01L23/36 , H01L23/3677 , H01L24/48 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/4824 , H01L2224/73265 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.
摘要翻译： 一种半导体器件，包括衬底，电源总线，热源电路，热敏电路以及衬底中的多个电导热导电通硅通孔（TSV）。 TSV电耦合到电力总线并且位于热源电路和热敏电路之间以吸收来自热源电路的热量。
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公开(公告)号：US20070269969A1
公开(公告)日：2007-11-22
申请号：US11419304
申请日：2006-05-19
申请人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
发明人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
IPC分类号： H01L21/22 , H01L21/38 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , Y10S438/942
摘要： Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
摘要翻译： 根据通过氧化可氧化材料层的侧壁形成的图案在半导体层中形成诸如翅片的结构。 在一个实施例中，在可氧化层中图案化源极/漏极图案结构和鳍状图案结构。 然后从在沟道图案结构的侧壁和源极/漏极图案结构的顶表面上生长氧化物的氧化过程掩蔽鳍状图案结构。 随后去除沟道图案结构的剩余可氧化材料，留下氧化物层的两个部分之间的孔。 这两个部分在一个实施例中用作用于图案化半导体层以形成两个散热片的掩模。 该图案化还使得源极/漏极结构连接到鳍片。
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