公开(公告)号：US20040023484A1

公开(公告)日：2004-02-05

申请号：US10292589

申请日：2002-11-13

Applicant: ProMOS Technologies, Inc.

Inventor： Chun-Che Chen ,  Tza-Hao Wang

IPC: H01L021/38

CPC classification number: H01L21/76808

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trenches in the dielectric layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底上提供介电层，在电介质层上提供第一光致抗蚀剂层，图案化和限定第一光致抗蚀剂层，蚀刻第一光致抗蚀剂层和电介质层以形成多个垂直开口 去除所述第一光致抗蚀剂层，在所述电介质层上沉积第二光致抗蚀剂层，其中所述第二光致抗蚀剂层填充所述多个垂直开口，仅去除沉积在所述电介质层上的所述第二光致抗蚀剂层的一部分，其中所述第二光致抗蚀剂层具有 在所述电介质层上的第一基本均匀的厚度，在所述第二光致抗蚀剂层上沉积抗反射涂层，在所述抗反射涂层上方提供第三光致抗蚀剂层，图案化和限定所述第三光致抗蚀剂层，以及蚀刻所述抗反射 涂层和第二光致抗蚀剂层 rm是电介质层中的多个沟槽。

公开(公告)号：US20040021162A1

公开(公告)日：2004-02-05

申请号：US10210031

申请日：2002-08-02

Applicant: ProMOS Technologies, Inc.

Inventor： Ting-Shing Wang

IPC: H01L027/108

CPC classification number: H01L27/10832 ,  H01L27/0207 ,  H01L27/10867 ,  H01L27/10888

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract translation: 一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极 形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

公开(公告)号：US20030236002A1

公开(公告)日：2003-12-25

申请号：US10376230

申请日：2003-03-03

Applicant: PROMOS TECHNOLOGIES INC.

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L021/20 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底具有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US20030161176A1

公开(公告)日：2003-08-28

申请号：US10189506

申请日：2002-07-08

Applicant: ProMOS Technologies Inc.

Inventor： Matthias Klaus

IPC: G11C011/22

CPC classification number: G11C29/026 ,  G11C29/02 ,  G11C2029/5004

Abstract: A method for measuring a bias voltage of plural sense amplifiers in a memory device is provided. The method includes the steps of: selecting the plural sense amplifiers as a measurement area, writing a midlevel voltage into the respective memory cell modules connected to the plural the sense amplifiers respectively, providing a reference voltage of the midlevel voltage into the plural sense amplifiers in the measurement area, recording output signals of the plural sense amplifiers, wherein the output signal is valued one of null0null and null1null, counting numbers of null0null and null1null, and obtaining a ratio of the number of null0null over the number of null1null, and obtaining the bias voltage of the plural sense amplifiers in the measurement area as the ratio.

公开(公告)号：US20030134468A1

公开(公告)日：2003-07-17

申请号：US10043477

申请日：2002-01-11

Applicant: ProMOS Technologies, Inc.

Inventor： Hsiao-Lei Wang ,  Chao-Hsi (Jesse) Chung ,  Hung-Kwei Liao

IPC: H01L021/8242 ,  H01L027/108

CPC classification number: H01L29/66181 ,  H01L27/1087 ,  H01L29/945

Abstract: A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.

Abstract translation: 已经开发了通过形成深的，宽直径的沟槽电容器结构来增加DRAM单元电容的方法。 下面的半导体衬底用于容纳深的，宽直径的沟槽电容器结构，而覆盖的，结合的，变薄的半导体衬底被用于适应窄直径的沟槽结构，然后又用于与下面的深沟槽电容器结构的通信，以及 容纳诸如传输门晶体管的DRAM器件的元件。 使用底层半导体衬底来容纳沟槽电容器结构允许使用更宽的直径结构，从而减少当形成窄直径的深沟槽电容器结构时遇到的图案化困难。

公开(公告)号：US20030109140A1

公开(公告)日：2003-06-12

申请号：US10020754

申请日：2001-12-12

Applicant: ProMOS Technologies, Inc.

Inventor： Brian Lee

IPC: H01L021/302 ,  H01L021/461 ,  H01L021/311

CPC classification number: H01L27/10867 ,  H01L21/76224

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device is described. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.

Abstract translation: 描述了在DRAM集成电路器件的制造中改进的掩埋带方法。 将深沟槽刻蚀成衬底。 在深沟槽的上部形成套环。 通过掺杂在深沟槽的下部周围形成掩埋板，并且在深沟槽内形成电容器电介质层。 深沟槽填充有硅层，其中硅层形成深沟槽电容器并覆盖套环。 硅层在衬底的顶表面下方凹入以留下凹槽。 将衣领的顶部蚀刻掉以留下衣领。 半球形晶粒多晶硅层被选择性地沉积到深沟槽中并填充套环。 HSG层原位掺杂或通过后等离子体掺杂。 掺杂的半球晶粒多晶硅层在深​​沟槽DRAM集成电路器件的制造中形成掩埋带。

公开(公告)号：US20030040176A1

公开(公告)日：2003-02-27

申请号：US10061562

申请日：2002-02-01

Applicant: ProMOS Technologies Inc.

Inventor： Ting-Sing Wang

IPC: H01L021/44 ,  H01L023/58

CPC classification number: H01L21/76897 ,  H01L22/34

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a first gate having spacers on the side, at least one contact window formed between the spacers, a first contact plug formed in the first contact window, and a first contact area connecting with the first contact plug; and at least two probing pads, formed in the semiconductor substrate, comprised of a plurality of second gates formed with spacers on the side, second contact windows exposing the second gates, a second contact plug formed in the second contact window, and a second contact area connecting with the first contact area. According to the present invention, defects are detected by electrical measurement immediately following the formation of contact plugs. Moreover, conventional processes can be used for the method for fabricating the inline detection device for self-aligned contact according to the invention. The detection device is formed simultaneously with the semiconductor device without extra process or steps.

Abstract translation: 本发明提供了一种形成在半导体衬底中的自对准接触缺陷的在线检测装置，包括：形成在半导体衬底中的有源区，包括在侧面具有间隔物的第一栅极，形成至少一个接触窗口 在所述间隔件之间，形成在所述第一接触窗口中的第一接触插塞和与所述第一接触插塞连接的第一接触区域; 以及形成在所述半导体衬底中的至少两个探测焊盘，包括形成在所述侧面上的间隔物的多个第二栅极，暴露所述第二栅极的第二接触窗口，形成在所述第二接触窗口中的第二接触插塞和第二接触 区域与第一接触区域连接。 根据本发明，在形成接触塞后立即通过电测量来检测缺陷。 此外，根据本发明，常规方法可用于制造用于自对准接触的在线检测装置的方法。 该检测装置与半导体器件同时形成，而无需额外的工艺或步骤。

公开(公告)号：US20020182862A1

公开(公告)日：2002-12-05

申请号：US09999453

申请日：2001-12-03

Applicant: ProMOS Technologies, Inc.

Inventor： Shi-Chung Sun ,  Hao-Yi Tsai

IPC: C23C014/32 ,  H01L021/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76864 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method of forming a tantalum carbide nitride diffusion barrier layer having optimized nitrogen concentration for improved thermal stability is described. A contact region is provided in a substrate. A via is opened through an insulating layer to the contact region. A tantalum carbide nitride barrier layer is deposited within the via wherein the tantalum carbide nitride layer has an optimized nitrogen content of between about 17% and 24% by atomic percentage. A layer of copper is deposited overlying the tantalum carbide nitride barrier layer to complete copper metallization in the fabrication of an integrated circuit device.

Abstract translation: 描述了一种形成具有优化的氮浓度以改善热稳定性的碳化钽氮化物扩散阻挡层的新方法。 接触区域设置在基板中。 通孔通过绝缘层打开到接触区域。 在通孔内沉积氮化钽氮化物阻挡层，其中碳化钽氮化物层具有约17％至24％原子百分比的最佳氮含量。 沉积在碳化钽氮化物阻挡层上的铜层，以在集成电路器件的制造中完成铜金属化。

公开(公告)号：US6391706B2

公开(公告)日：2002-05-21

申请号：US81635601

申请日：2001-03-26

Applicant: PROMOS TECHNOLOGIES INC ,  MOSEL VITELIC INC ,  INFINEON TECHNOLOGIES INC

Inventor： WU CHAO-CHUEH ,  CHIU SHENG-FEN ,  CHUNG JESSE ,  WANG HSIAO-LEI

IPC: H01L21/8242

CPC classification number: H01L27/1087

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si3N4) uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract translation: 实现了一种用于在晶片边缘处制造具有减小的沟槽刻面的DRAM电路的改进的深沟槽电容器以及用于提高工艺产量的改进的焊盘氮化硅（Si 3 N 4）均匀性的方法。 该方法利用较厚的焊盘Si 3 N 4作为用于蚀刻深沟槽的硬掩模的一部分。 然后，在通过一系列工艺步骤形成深沟槽电容器之后，形成浅沟槽隔离（STI）。 该方法利用在较厚的焊盘Si3N4层中蚀刻浅沟槽并进入硅衬底。 将第二绝缘层沉积并抛光（CMP）到焊盘Si3N4层中。 一个关键特征是使用第二掩模来保护衬底中心，同时部分地蚀刻由固化地由CMP产生的衬底边缘处的衬垫Si3N4层的较厚部分。 这使焊盘Si3N4层的不均匀性最小化，以提供用于进一步处理的更可靠的结构。

公开(公告)号：US20020058410A1

公开(公告)日：2002-05-16

申请号：US09817934

申请日：2001-03-27

Applicant: ProMOS Technologies, Inc.

Inventor： Ben Sung ,  Heng-Kai Hsu

IPC: H01L021/336 ,  H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/321 ,  H01L21/28061 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of prohibiting from producing a protrusion alongside a silicide layer of a gate unit is disclosed. The method includes steps of (a) providing a chamber and a semiconductor wafer having the gate unit thereon, (b) loading the semiconductor wafer into the chamber, (c) providing a mixing gas of nitrogen gas and hydrogen gas into the chamber and performing a rapid thermal anneal (RTA) step for the gate unit, and (d) performing a rapid thermal oxidation (RTO) step for the gate unit. Alternatively, the method includes steps of (a) providing a first chamber and a semiconductor wafer having a gate unit thereon, (b) loading the semiconductor wafer into the first chamber and purging oxygen gas therein, (c) performing a rapid thermal anneal (RTA) step for the gate unit, and (d) performing a rapid thermal oxidation (RTO) step for the gate unit.

Abstract translation: 公开了一种禁止在栅极单元的硅化物层旁边产生突起的方法。 该方法包括以下步骤：（a）在其上提供具有栅极单元的腔室和半导体晶片，（b）将半导体晶片装载到腔室中，（c）将氮气和氢气的混合气体提供到腔室中并执行 用于栅极单元的快速热退火（RTA）步骤，以及（d）对栅极单元执行快速热氧化（RTO）步骤。 或者，该方法包括以下步骤：（a）提供在其上具有栅极单元的第一室和半导体晶片，（b）将半导体晶片装载到第一室中并在其中吹扫氧气;（c）执行快速热退火 RTA）步骤，以及（d）对门单元执行快速热氧化（RTO）步骤。