公开(公告)号：US09124388B2

公开(公告)日：2015-09-01

申请号：US13893475

申请日：2013-05-14

Applicant: ST-Ericsson SA

Inventor： Elias Jonsson

IPC: H04L5/00

CPC classification number: H04L5/0007 ,  H04B17/327 ,  H04L5/0048

Abstract: A Reference Signal Received Power (RSRP) value is produced from a received Orthogonal Frequency Division Multiplexed (OFDM) signal that comprises a plurality of reference symbols located at known sub-carrier frequencies and times within the received OFDM signal. RSRP value production involves, for each hypothesized error state selected from a plurality of different hypothesized error states, ascertaining a corresponding hypothesized RSRP value, and then using the hypothesized RSRP values as a basis for determining a value for use as the produced RSRP value (e.g., by selecting a maximum one of the hypothesized RSRP values as the produced RSRP value). In this technology, each of the hypothesized error states is a hypothesized frequency error paired with a hypothesized timing error and the corresponding hypothesized RSRP value is produced by adjusting one or more measured channel estimates as a function of the hypothesized error state.

Abstract translation: 从接收到的正交频分复用（OFDM）信号产生参考信号接收功率（RSRP）值，所述正交频分复用（OFDM）信号包括位于接收的OFDM信号中的已知子载波频率和时间的多个参考符号。 对于从多个不同的假设错误状态中选出的每个假设错误状态，确定相应的假设的RSRP值，然后使用假定的RSRP值作为确定用作所产生的RSRP值的值的基础（例如， 通过选择假设的RSRP值中的最大值作为产生的RSRP值）。 在该技术中，每个假设的误差状态是与假设的定时误差配对的假设频率误差，并且通过将一个或多个测量的信道估计值调整为假设的误差状态的函数来产生相应的假设的RSRP值。

公开(公告)号：US09094040B2

公开(公告)日：2015-07-28

申请号：US14368040

申请日：2012-12-29

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H03M3/00 ,  H03M1/06

CPC classification number: H03M3/462 ,  H03M1/06 ,  H03M3/394 ,  H03M3/414 ,  H03M3/436 ,  H03M3/496

Abstract: A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract translation: 连续时间的MASHΣ-Δ模数转换器ADC。 ADC可以包括第一和第二调制器和输出级。 ADC可以设置有具有1.5位的第一调制器和具有1位的第二调制器，每个还接收来自另一个调制器的反馈。 在第二调制器处采样速率较高，并且在将其输出与第一调制器的输出相加之前进行抽取。

公开(公告)号：US20150208328A1

公开(公告)日：2015-07-23

申请号：US14378752

申请日：2013-03-12

Applicant: ST-Ericsson SA

Inventor： Oskar Drugge ,  Koichi Kojima ,  Max Larsson ,  Torgny Palenius ,  Benny Stenlund

IPC: H04W48/16 ,  H04W88/08 ,  H04W56/00

CPC classification number: H04W48/16 ,  H04B1/7083 ,  H04B1/7087 ,  H04J11/0086 ,  H04L27/2657 ,  H04L27/2686 ,  H04W56/00 ,  H04W88/08

Abstract: A receiver 10 and method in the receiver for cell search to find an actual base station having a carrier frequency in a radio communications network 1. The receiver detects a first signal representative of a base station 12, 14, 16, 18 by performing slot synchronisation, frame synchronization, cell identification, measurement of a signal quality of the first signal and comparison of the measured signal quality with a first threshold value. When a first signal having a signal quality that is greater than the first threshold value has been detected, the receiver searches for at least one second signal representative of a base station for at least one frequency offset comprised in a set of offsets S3. Further, when one or more second signals are detected, the receiver selects the signal with the highest signal quality, and detects a broadcast radio channel representative of a base station for the selected signal.

Abstract translation: 用于小区搜索的接收机中的接收机10和方法，用于在无线电通信网络1中找到具有载波频率的实际基站。接收机通过执行时隙同步来检测代表基站12,14,16,18的第一信号 ，帧同步，小区识别，第一信号的信号质量的测量以及所测量的信号质量与第一阈值的比较。 当已经检测到具有大于第一阈值的信号质量的第一信号时，接收机针对包括在一组偏移量S3中的至少一个频率偏移量，搜索表示基站的至少一个第二信号。 此外，当检测到一个或多个第二信号时，接收机选择具有最高信号质量的信号，并且检测表示所选信号的基站的广播无线电信道。

公开(公告)号：US20150207656A1

公开(公告)日：2015-07-23

申请号：US14420791

申请日：2013-09-03

Applicant: ST-Ericsson SA

Inventor： Achraf Dhayni

IPC: H04L27/26

CPC classification number: H04L27/2623 ,  H04L27/2624

Abstract: An emitter for modulating and emitting an orthogonal frequency division multiplexing signal through a transmission channel (TC), comprising a frequency-to-time converter for converting symbols to be transmitted into time symbols, and means for serializing and amplifying said time symbol so as to emit it as an OFDM signal through said transmission channel, said emitter further comprising: means (12) for clipping said time symbols; time-to-frequency convertor (13) for converting said time symbols; and means for applying a set of data subcarriers of the outputs of said time-to-frequency converter as inputs of said frequency-to-time converter wherein out-of-band subcarriers are set to zero and the clipping level is set to a minimum level allowing the amplifier to operate in an efficient region.

Abstract translation: 一种用于通过传输信道（TC）调制和发射正交频分复用信号的发射器，包括用于将要发送的符号转换为时间符号的频率 - 时间转换器，以及用于串行化和放大所述时间符号的装置，以便 通过所述传输信道将其发射为OFDM信号，所述发射器还包括：用于剪切所述时间符号的装置（12）; 时间 - 频率转换器（13），用于转换所述时间符号; 以及用于将所述时间 - 频率转换器的输出的一组数据子载波应用于所述频率 - 时间转换器的输入的装置，其中带外子载波被设置为零，并且限幅电平被设置为最小 电平允许放大器在有效的区域中工作。

公开(公告)号：US20150155841A1

公开(公告)日：2015-06-04

申请号：US14402003

申请日：2013-05-24

Applicant: ST-Ericsson SA

Inventor： Andrea Barbieri ,  Germano Nicollini

IPC: H03F3/45 ,  H03M1/18 ,  H03F3/21

CPC classification number: H03F3/45071 ,  H03F1/0261 ,  H03F3/21 ,  H03F3/3023 ,  H03F3/45183 ,  H03F2200/153 ,  H03F2200/411 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/513 ,  H03F2203/45134 ,  H03F2203/45192 ,  H03F2203/45644 ,  H03F2203/45658 ,  H03M1/183

Abstract: The invention relates to a two-stage operational amplifier (400) in class AB for driving a load (RLB, RLA) comprising: an input stage (401) comprising differential input terminals (IN, lp) and a first differential output terminal (O1P) and a second differential output terminal (O1N) for providing a first differential driving signal (Out1P) and a second differential driving signal (Out1N), respectively; an output stage (402) comprising a first output branch (403) having a first differential input terminal (I1P) operatively connected to the first differential output terminal (O1P) of the input stage (401) to receive the first differential driving signal (OUT1P) and a second output branch (404) having a second differential input terminal (I1N) operatively connected to the second differential output terminal (O1N) of the output stage (401) to receive the second differential driving signal (Out1N), a control circuit (405) configured to control the output stage (402).

Abstract translation: 本发明涉及用于驱动负载（RLB，RLA）的AB类中的两级运算放大器（400），包括：输入级（401），包括差分输入端（IN，lp）和第一差分输出端（O1P ）和用于分别提供第一差分驱动信号（Out1P）和第二差分驱动信号（Out1N）的第二差分输出端子（O1N） 输出级（402），包括具有可操作地连接到输入级（401）的第一差分输出端（O1P）的第一差分输入端（I1P）的第一输出分支（403），以接收第一差分驱动信号（OUT1P ）和具有与输出级（401）的第二差分输出端子（O1N）可操作地连接以接收第二差分驱动信号（Out1N）的第二差分输入端子（I1N）的第二输出分支（404），控制电路 （405），被配置为控制所述输出级（402）。

公开(公告)号：US20150139360A1

公开(公告)日：2015-05-21

申请号：US14401183

申请日：2013-06-18

Applicant: ST-Ericsson SA

Inventor： Hendrik Visser ,  Roeland Heijna

IPC: H04L27/36 ,  H04B14/00 ,  H04W52/02

CPC classification number: H04L27/36 ,  H03C5/00 ,  H04B14/008 ,  H04L27/361 ,  H04W52/0209 ,  Y02D70/122

Abstract: A polar modulator (200) comprises a modulation generator (10) arranged to generate phase modulation data and amplitude modulation data; and a phase modulation stage (20) arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data, and the phase modulation stage (20) comprises an adjustable delay stage (50) arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value. The polar modulator (200) further comprises a re-timing circuit (40) arranged to generate an amplitude modulation, AM, clock signal by re-timing the PM clock signal with the PM carrier signal; an amplitude modulation stage (30) arranged to employ the AM clock signal to clock the amplitude modulation data into the amplitude modulation stage (30) and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data; an error detection stage (60) arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage (70) arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage (50), a first value of the relative delay that maximises the magnitude of the first deviation, and applying an offset to the first value of the relative delay.

Abstract translation: 极性调制器（200）包括调制发生器（10），其被配置为产生相位调制数据和幅度调制数据; 以及相位调制级（20），被配置为产生相位调制PM载波信号和PM时钟信号，其中所述PM载波信号具有PM载波信号频率，并且所述PM时钟信号具有PM时钟信号频率，并且 PM载波信号频率高于PM时钟信号频率，PM载波信号和PM时钟信号由相位调制数据相位调制，相位调制级（20）包括可调节延迟级（50），其被布置为调整 PM载波信号和PM时钟信号之间的相对延迟达到目标值。 极性调制器（200）还包括重新定时电路（40），其被布置成通过用PM载波信号重新定时PM时钟信号来产生幅度调制AM时钟信号; 幅度调制级（30），被配置为使用所述AM时钟信号将所述幅度调制数据时钟调制到所述幅度调制级（30）中，并且被布置成用所述振幅调制数据对所述PM载波信号进行幅度调制; 错误检测级（60），被配置为产生AM时钟信号与目标条件的第一偏差量值的指示; 以及控制级（70），其被布置为通过通过控制所述可调节延迟级（50）的所述相对延迟的调整来确定所述相对延迟的目标值，所述相对延迟的第一值使所述相对延迟的幅度最大化 第一偏差，并且将偏移应用于相对延迟的第一值。

公开(公告)号：US20150108225A1

公开(公告)日：2015-04-23

申请号：US14405216

申请日：2013-06-19

Applicant: ST-Ericsson SA

Inventor： Pablo Ignacio Gimeno Monge ,  Javier Del Prado Pavon ,  Nikhil Taluja

IPC: G06K19/07 ,  H02J9/06

CPC classification number: G06K19/0703 ,  G06K19/0702 ,  G06K19/0712 ,  G06K19/0715 ,  G06K19/0727 ,  H02J9/061

Abstract: There is described a method of and a circuit for supplying power to an integrated circuit card, ICC, of a wireless device comprising a first power supply unit. The circuit comprises a power pin connected configured to selectively operate as a power input pin or as a power output pin, and adapted to be connected to the first power path of the device through a second power path of the device; a second power supply unit; and a controller configured to cause the power pin to operate as a power input pin in the first operation mode of the device, or as a power output pin in the second operation mode of the device. A wireless device comprising the circuit and a method of supplying power to an ICC are further disclosed.

Abstract translation: 描述了一种用于向包括第一电源单元的无线设备的集成电路卡ICC供电的方法和电路。 该电路包括被配置为选择性地操作为电源输入引脚或作为电源输出引脚的电源引脚，并且适于通过该器件的第二电源路径连接到器件的第一电源通路; 第二电源单元; 以及控制器，被配置为使得所述电源引脚在所述器件的第一操作模式下作为电源输入引脚工作，或者作为所述器件的第二操作模式中的电源输出引脚。 还公开了一种包括电路的无线设备和向ICC供电的方法。

公开(公告)号：US08976840B2

公开(公告)日：2015-03-10

申请号：US14291049

申请日：2014-05-30

Applicant: ST-Ericsson SA

Inventor： Kazuyoshi Uesaka ,  Elias Jonsson ,  Hisashi Onozawa

IPC: H04B1/00 ,  H04B1/7117

CPC classification number: H04B1/7117 ,  H04B1/7113

Abstract: The method disclosed herein is implemented in a radio receiver to detect an AWGN channel, where the radio receiver comprises a rake receiver. The radio receiver receives signals transmitted via a propagation channel from a transmitter, and determines that the propagation channel is an AWGN channel when a filtered version of a minimum value of a metric is lower than a threshold value. The metric relates to a difference between a normalized measured power profile of the propagation channel and a normalized power template, which normalized power template is dependent on predetermined sampling timing shifts and on rake finger positions within the rake receiver.

Abstract translation: 本文公开的方法在无线电接收机中实现以检测AWGN信道，其中无线电接收机包括耙式接收机。 无线电接收机接收从发射机经由传播信道传输的信号，并且当度量的最小值的滤波版本低于阈值时，确定传播信道是AWGN信道。 该度量涉及传播信道的归一化测量功率分布与归一化功率模板之间的差异，该归一化功率模板取决于预定采样定时偏移和耙机接收机内的耙指位置。

公开(公告)号：US08963755B2

公开(公告)日：2015-02-24

申请号：US14351111

申请日：2012-10-10

Applicant: ST-Ericsson SA

Inventor： Carlo Pinna

IPC: H03M3/00

CPC classification number: H03M3/30 ,  H03M3/39 ,  H03M3/424 ,  H03M3/454

Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径，其包括计算块，模拟积分器，数字积分器和具有降低的量化级别的量化器。 此外，转换器包括反馈路径，其被布置为向计算块提供反馈模拟信号。 反馈模拟信号通过反馈路径和计算块直接在量化器的输入端注入。 该转换器允许降低量化器的复杂性。

公开(公告)号：US20150035591A1

公开(公告)日：2015-02-05

申请号：US14379399

申请日：2013-02-26

Applicant: ST-Ericsson SA

Inventor： Germano Nicollini ,  Andrea Barbieri

IPC: G05F3/26 ,  H03H7/01

CPC classification number: G05F3/262 ,  G05F1/56 ,  G05F1/561 ,  G05F3/26 ,  H03H7/0161

Abstract: A low-noise reference voltages distribution circuit (10) is disclosed, comprising a multi-output voltage to current converter (V/I_Conv) adapted to receive an input reference voltage (VR) for providing a plurality of output reference currents (I1, . . . , IN) to be converted into a plurality of local reference voltages (V01, V0N) at corresponding receiving circuits (LCR1, LCRN) adapted to be connected to said reference voltages distribution circuit (10). The multi-output voltage to current converter (V/I_Conv) comprises: -an input section (20) adapted to generate on the basis of said input reference voltage (VR) a reference current (I0), the input section (20) comprising a current mirror input transistor (M0E) having a voltage controlled input terminal (g0E); -an output section (50) comprising a plurality of current mirror output transistors (M01, M0N) each adapted to provide a corresponding output reference current of said plurality of reference currents (I1, . . . , IN), each of said current mirror output transistors (M01, M0N) comprising a voltage controlled input terminal (g01, . . . , g0N), the output section (50) comprising a common input node (51) to which voltage controlled input terminals (g01, g0N) of said current mirror output transistors (M01, M0N) are connected. The voltage to current converter (V/I_Conv) comprises a low-pass filter (30) having an input node (31) connected to said voltage controlled input terminal (g0E) of the current mirror input transistor (M0E) and an output node (33) connected to said common input node (51).

Abstract translation: 公开了一种低噪声参考电压分配电路（10），其包括适于接收用于提供多个输出参考电流（I1，...）的输入参考电压（VR）的多输出电压 - 电流转换器（V / I_Conv）。 ...，IN）在适于连接到所述参考电压分配电路（10）的相应接收电路（LCR1，LCRN）处被转换成多个局部参考电压（V01，V0N）。 多输出电压到电流转换器（V / I_Conv）包括： - 适于基于所述输入参考电压（VR）产生参考电流（I0）的输入部分（20），所述输入部分（20）包括 具有电压控制输入端（g0E）的电流镜输入晶体管（M0E）; - 输出部分（50），包括多个电流镜输出晶体管（M01，M0N），每个电流镜输出晶体管适于提供所述多个参考电流（I1，...，IN）的相应的输出参考电流，每个所述电流镜 输出晶体管（M01，M0N），包括电压控制输入端（g01，...，g0N），输出部分（50）包括公共输入节点（51），所述输入端 电流镜输出晶体管（M01，M0N）连接。 电压 - 电流转换器（V / I_Conv）包括具有连接到电流镜输入晶体管（M0E）的所述电压控制输入端子（g0E）的输入节点（31）的低通滤波器（30）和输出节点 33）连接到所述公共输入节点（51）。