公开(公告)号：US12061530B2

公开(公告)日：2024-08-13

申请号：US17655103

申请日：2022-03-16

申请人： STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

发明人： Roberto Colombo ,  Vivek Mohan Sharma

IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/273

CPC分类号： G06F11/2273 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/2733

摘要： A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

公开(公告)号：US20240171424A1

公开(公告)日：2024-05-23

申请号：US18509618

申请日：2023-11-15

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics (Alps) SAS

发明人： Fred Rennig ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Philippe Sirito-Olivier ,  Fritz Burkhardt ,  Aldo Occhipinti

IPC分类号： H04L12/40

CPC分类号： H04L12/40006 ,  H04L2012/40215

摘要： A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.

公开(公告)号：US20240160598A1

公开(公告)日：2024-05-16

申请号：US18503744

申请日：2023-11-07

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

发明人： Mirko Dondini ,  Calogero Andrea Trecarichi ,  Fred Rennig

IPC分类号： G06F13/42

CPC分类号： G06F13/4282 ,  G06F2213/40

摘要： An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

公开(公告)号：US11921910B2

公开(公告)日：2024-03-05

申请号：US17443497

申请日：2021-07-27

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

发明人： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC分类号： G06F21/83 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/32 ,  H04L9/40 ,  H04W4/40 ,  H04W12/03 ,  H04W12/106 ,  H04W12/40

CPC分类号： G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G09C1/00 ,  H04L9/3234 ,  H04W12/106 ,  G06F2212/7209 ,  H04L63/0853 ,  H04W4/40 ,  H04W12/03 ,  H04W12/40

摘要： A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

公开(公告)号：US20240021604A1

公开(公告)日：2024-01-18

申请号：US18478465

申请日：2023-09-29

申请人： STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

发明人： Mathieu ROUVIERE ,  Arnaud YVON ,  Mohamed SAADNA ,  Vladimir SCARPA

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

摘要： A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

公开(公告)号：US20230349969A1

公开(公告)日：2023-11-02

申请号：US18186549

申请日：2023-03-20

申请人： STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

发明人： Roberto Colombo ,  Vivek Mohan Sharma ,  Samiksha Agarwal

IPC分类号： G01R31/317

CPC分类号： G01R31/31703 ,  G01R31/31722

摘要： In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

公开(公告)号：US11782095B2

公开(公告)日：2023-10-10

申请号：US17368198

申请日：2021-07-06

申请人： STMicroelectronics Application GMBH

发明人： Markus Ekler

IPC分类号： G01R31/382 ,  G01R31/396 ,  G01R31/367 ,  B60L58/12 ,  H01M10/42

CPC分类号： G01R31/382 ,  B60L58/12 ,  G01R31/367 ,  G01R31/396 ,  H01M10/4257 ,  H01M2010/4271 ,  H01M2220/20

摘要： An embodiment processing system comprises terminals configured to be connected to cells of a rechargeable battery to receive cell voltages, a digital processing circuit, a serial communication interface and a transmission queue interfacing the digital processing circuit with the serial communication interface for parallel operation. The digital processing circuit synchronously acquires a given number of digital samples of each of the cell voltages and stores them to a memory. The digital processing circuit encodes the digital samples stored to the memory via a data compression module, and stores the encoded data to the transmission queue. For example, the data compression module may generate the encoded data by subtracting a given offset from each digital sample to generate values indicative of the dynamic variation of each sample with respect to the offset, and removing a given number of most significant bits from each value.

公开(公告)号：US20230299999A1

公开(公告)日：2023-09-21

申请号：US18320764

申请日：2023-05-19

申请人： STMICROELECTRONICS APPLICATION GMBH

发明人： Fred RENNIG ,  Rolf NANDLINGER

IPC分类号： H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC分类号： H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

摘要： A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US11755062B2

公开(公告)日：2023-09-12

申请号：US17933680

申请日：2022-09-20

申请人： STMicroelectronics Application GMBH

发明人： Rolf Nandlinger

IPC分类号： G06F1/14

CPC分类号： G06F1/14

摘要： A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US20220357973A1

公开(公告)日：2022-11-10

申请号：US17736590

申请日：2022-05-04

申请人： STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

发明人： Boris VITTORELLI ,  Simrata BATRA ,  Vivek Kumar SOOD ,  Deepak BARANWAL

IPC分类号： G06F9/455

摘要： A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.