公开(公告)号：US20060015788A1

公开(公告)日：2006-01-19

申请号：US11206170

申请日：2005-08-18

Applicant: Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

Inventor： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G11C29/48 ,  G11C29/36

Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.

公开(公告)号：US06961881B2

公开(公告)日：2005-11-01

申请号：US10122181

申请日：2002-04-16

Applicant: Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

Inventor： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

IPC: G11C29/00 ,  G11C29/36 ,  G11C29/48

CPC classification number: G11C29/48 ,  G11C29/36

Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

Abstract translation: 由逻辑芯片访问的逻辑芯片和存储器芯片安装在单个封装中。 逻辑芯片的模式发生器在第一测试模式下操作以产生用于存储器芯片的内部测试模式。 模式选择器在第一测试模式期间选择从模式发生器输出的内部测试模式，在第二测试模式期间，选择通过测试终端提供的外部测试模式，并将所选择的测试模式输出到存储芯片。 通过使用模式选择信号，在第二测试模式中使用在逻辑芯片内产生的第一测试模式中的内部测试模式或外部测试模式来测试安装在封装中的存储芯片， 从外部。

公开(公告)号：US06819610B2

公开(公告)日：2004-11-16

申请号：US10267873

申请日：2002-10-10

Applicant: Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto ,  Ayako Sato ,  Masato Matsumiya

Inventor： Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto ,  Ayako Sato ,  Masato Matsumiya

IPC: G11C700

CPC classification number: G11C7/12 ,  G11C11/4094

Abstract: A semiconductor memory device includes a first bit line connected to a memory cell via a transistor, a transfer gate, a second bit line connected to the first bit line via the transfer gate, a sense amplifier connected to the second bit line, a first precharge circuit for precharging the first bit line, a second precharge circuit for precharging the second bit line, a control circuit which precharges the first bit line by the first precharge circuit after closing the transfer gate, followed by subsequent precharging of the second bit line by the second precharge circuit.

Abstract translation: 半导体存储器件包括经由晶体管连接到存储单元的第一位线，传输门，经由传输门连接到第一位线的第二位线，连接到第二位线的读出放大器，第一预充电 用于对第一位线进行预充电的电路，用于对第二位线进行预充电的第二预充电电路，在关闭传输门之后由第一预充电电路对第一位线进行预充电的控制电路，随后通过第二位线预先充电第二位线 第二预充电电路。

公开(公告)号：US06753695B2

公开(公告)日：2004-06-22

申请号：US10104069

申请日：2002-03-25

Applicant: Haruki Toda ,  Kenji Tsuchida ,  Satoshi Eto ,  Kuninori Kawabata

Inventor： Haruki Toda ,  Kenji Tsuchida ,  Satoshi Eto ,  Kuninori Kawabata

IPC: H03K3017

CPC classification number: H03K5/13 ,  H03K5/06 ,  H03K5/08

Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.

Abstract translation: 半导体集成电路器件包括多个MIS晶体管，以及集成电路单元，其包括由多个MIS晶体管的组合构成的逻辑门电路。 每个MIS晶体管具有包括由电容和电阻并联连接的等效电路表示的电路元件的栅极。

公开(公告)号：US06707325B2

公开(公告)日：2004-03-16

申请号：US10278080

申请日：2002-10-23

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshihiro Takemae ,  Hiroshi Yoshioka ,  Makoto Koga

IPC: H03K300

CPC classification number: H03K19/018585

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

公开(公告)号：US06630850B2

公开(公告)日：2003-10-07

申请号：US09538721

申请日：2000-03-30

Applicant: Satoshi Eto ,  Satoru Saitoh ,  Shinichi Yamada

Inventor： Satoshi Eto ,  Satoru Saitoh ,  Shinichi Yamada

IPC: H03L700

CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C7/1087

Abstract: A delay circuit and a plurality of accepting circuits are comprised. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is adjusted to optimize an accepting timing to an input signal by a clock signal in each of the accepting circuit. The each accepting circuit reliably accepts the delayed input signal respectively in synchronization with a clock signal. Therefore, it is unnecessary to respectively provide a delay circuit in the plurality of the accepting circuits. As a result, the plurality of accepting circuits can reliably accept input signals without enlarging a circuit scale. A plurality of delay circuits, a plurality of accepting circuits, and an operating circuit are comprised. The delay circuit receives a plurality of input signals, and outputs each of the delayed input signals respectively to the plurality of accepting circuits. The accepting circuit accepts the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of the each delay circuit, for example, is in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin.

Abstract translation: 包括延迟电路和多个接受电路。 由外部提供的输入信号由延迟电路延迟预定的时间长度，然后被分配并输出到多个接收器电路。 调整延迟电路的延迟时间，以通过每个接收电路中的时钟信号来优化对输入信号的接受定时。 每个接收电路可以与时钟信号同步地可靠地接受延迟的输入信号。 因此，不需要在多个接受电路中分别提供延迟电路。 结果，多个接受电路可以可靠地接受输入信号而不放大电路规模。 包括多个延迟电路，多个接受电路和操作电路。 延迟电路接收多个输入信号，并且分别将多个延迟输入信号输出到多个接受电路。 接受电路与时钟信号同步地接受延迟的输入信号。 多个延迟的输入信号被提供给操作电路以执行逻辑操作。 例如，每个延迟电路的延迟时间与提供给操作电路的输入信号的提供时序相一致。 结果，操作电路以足够的定时裕度执行逻辑运算。

公开(公告)号：US06384671B1

公开(公告)日：2002-05-07

申请号：US09541699

申请日：2000-04-03

Applicant: Masao Taguchi ,  Satoshi Eto ,  Yoshinori Okajima

Inventor： Masao Taguchi ,  Satoshi Eto ,  Yoshinori Okajima

IPC: G05F110

CPC classification number: H04L25/0278 ,  H03K17/16 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract translation: 具有总线，从总线分支的多个短截线的电子电路装置以及具有连接到对应短线的信号输入/输出端子的多个半导体器件。 电子电路装置包括布置在总线和至少一个短截线之间的至少一个阻抗电路，并且每个阻抗电路具有高通滤波器特性。 因此，抑制振铃，防止传输信号的高频分量的衰减，维持信号的定义，并且提高传输频率和速度。

公开(公告)号：US06252269B1

公开(公告)日：2001-06-26

申请号：US09422860

申请日：1999-10-25

Applicant: Masatomo Hasegawa ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii

Inventor： Masatomo Hasegawa ,  Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii

IPC: H01L27108

CPC classification number: H01L21/8249 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/105 ,  H01L27/10897

Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Abstract translation: 根据本发明的一个方面的半导体存储器，在形成在P型半导体衬底的表面的P型第一阱区域中形成存储单元晶体管，并且将反向偏置电压施加到 P型第一阱区和P型衬底。 此外，通过注入高能N型杂质形成N型逆行区域，从而通过采用N型逆行区域形成较深的N型第二阱区域。 此外，在N型第二阱区中形成P型第三阱区，并且还在其中形成P型发射极区。 因此，P型发射极区域，N型第二阱区域和P型第三阱区域一起构成横向PNP晶体管。 此外，为作为集电极区域的P型第三阱区域保持接地电压。

公开(公告)号：US06229363B1

公开(公告)日：2001-05-08

申请号：US09224354

申请日：1999-01-04

Applicant: Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

Inventor： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC: H03L708

CPC classification number: G11C7/1057 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

Abstract translation: 具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。 具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时， 第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

公开(公告)号：US06195304B1

公开(公告)日：2001-02-27

申请号：US09500814

申请日：2000-02-10

Applicant: Satoshi Eto ,  Masato Matsuyima ,  Kuninori Kawabata ,  Akira Kikutake

Inventor： Satoshi Eto ,  Masato Matsuyima ,  Kuninori Kawabata ,  Akira Kikutake

IPC: G11C700

CPC classification number: G11C11/406

Abstract: A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load. A refresh address counter outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load. A selector is provided to connect the refresh address counter outputs to the memory cell array, and assigns the predetermined high/low-state change periods for the respective bit signals of the refresh address signal in accordance with a correspondence between the bit signals and the capacitive loads. A refresh address signal generating method is also disclosed for use in the semiconductor memory device.

Abstract translation: 半导体存储器件包括具有以矩形或矩形形式配置的多个存储器单元的存储单元阵列，该存储单元阵列具有在不同存储位置上不同的预定容性负载，该容性负载包括最小电容负载和最大电容负载 容性负载。 刷新地址计数器输出构成刷新地址信号的多个位信号，刷新地址信号指示要在存储器件中刷新的存储单元的地址，具有预定的高/低状态改变周期的位信号是 不同的是，位信号包括对应于最小容性负载的第一位信号和对应于最大容性负载的第二位信号。 提供选择器以将刷新地址计数器输出连接到存储单元阵列，并根据比特信号和电容的对应关系为刷新地址信号的各个比特信号分配预定的高/低状态改变周期 负载 还公开了一种在半导体存储器件中使用的刷新地址信号产生方法。