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    Phase change random access memory device having variable drive voltage circuit
    31.
    发明申请
    Phase change random access memory device having variable drive voltage circuit 有权

    公开(公告)号：US20070058425A1

    公开(公告)日：2007-03-15

    申请号：US11316256

    申请日：2005-12-23

    申请人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

    发明人： Woo-yeong Cho ,  Du-eung Kim ,  Kwang-jin Lee ,  Choong-keun Kwak

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A phase change memory device includes a memory array including a plurality of phase change memory cells, each phase change memory cell including a phase change material and a diode, a plurality of column selection transistors connecting bit lines connected to the phase change memory cells to corresponding data lines, and a control node connecting the data lines to a sense amplifier unit. In a write operation mode, control voltages obtained by boosting a first voltage are respectively applied to the control node and gates of the column selection transistors, and a ground voltage is applied to a word line of a selected one of the phase change memory cells. In a standby mode, word lines and bit lines connected to the phase change memory cells of the memory array are maintained at the same voltage. According to the phase change memory device and a driving method thereof, a sufficient write voltage is supplied to a write driver, a column decoder and a row decoder in the write operation mode, and a voltage lower is applied to the write driver, the column decoder and the row decoder in the read operation mode and the standby mode, thereby reducing current consumption and enhancing operational reliability.

    Device and method for pulse width control in a phase change memory device
    32.
    发明授权
    Device and method for pulse width control in a phase change memory device 失效
    相变存储器件中脉冲宽度控制的装置和方法

    公开(公告)号：US07180771B2

    公开(公告)日：2007-02-20

    申请号：US11405993

    申请日：2006-04-18

    申请人： Woo-yeong Cho ,  Kyung-hee Kim

    发明人： Woo-yeong Cho ,  Kyung-hee Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C7/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2013/0066 ,  G11C2013/0092

    摘要： A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

    摘要翻译： 描述了用于编程相变存储器件（例如硫族化物存储器（PRAM））的电路和方法。 本发明涉及将PRAM元件从复位状态编程到设置状态或从设置状态到设置状态的方法。 本发明提供了一种新颖且不显而易见的PRAM器件和方法，其中通过在编程期间监视存储元件的状态来控制设定脉冲持续时间，例如通过将位线的电压与参考电压进行比较或将电池电阻与 设定状态电池电阻。 响应于检测到的存储元件的状态来控制设定脉冲的持续时间。 本发明的方法的结果是PRAM编程错误的显着降低，例如由恒定持续时间设置脉冲引起的错误，以及减少编程持续时间和功耗。

    Nonvolatile semiconductor memory device with scalable two transistor memory cells
    33.
    发明授权
    Nonvolatile semiconductor memory device with scalable two transistor memory cells 有权
    具有可伸缩双晶体管存储单元的非易失性半导体存储器件

    公开(公告)号：US07113425B2

    公开(公告)日：2006-09-26

    申请号：US10976626

    申请日：2004-10-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C11/404

    摘要： A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the selected data line. Operation speed is increased, while improving device cell array structure.

    摘要翻译： 非易失性存储器件包括位线，一对数据线和多个可伸缩双晶体管存储器（STTM）单元。 存储单元布置在一对数据之间，以便共享位线。 存储器件还包括数据线选择电路和读出放大电路。 数据线选择电路选择一对数据线之一，并且感测放大电路感测并放大位线与所选数据线之间的电压差。 操作速度提高，同时提高器件单元阵列结构。

    Device and method for pulse width control in a phase change memory device
    34.
    发明授权
    Device and method for pulse width control in a phase change memory device 有权
    相变存储器件中脉冲宽度控制的装置和方法

    公开(公告)号：US07085154B2

    公开(公告)日：2006-08-01

    申请号：US10773901

    申请日：2004-02-06

    申请人： Woo-yeong Cho ,  Kyung-hee Kim

    发明人： Woo-yeong Cho ,  Kyung-hee Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C7/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2013/0066 ,  G11C2013/0092

    摘要： A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

    摘要翻译： 描述了用于编程相变存储器件（例如硫族化物存储器（PRAM））的电路和方法。 本发明涉及将PRAM元件从复位状态编程到设置状态或从设置状态到设置状态的方法。 本发明提供了一种新颖且不显而易见的PRAM器件和方法，其中通过在编程期间监视存储元件的状态来控制设定脉冲持续时间，例如通过将位线的电压与参考电压进行比较或将电池电阻与 设定状态电池电阻。 响应于检测到的存储元件的状态来控制设定脉冲的持续时间。 本发明的方法的结果是PRAM编程错误的显着降低，例如由恒定持续时间设置脉冲引起的错误，以及减少编程持续时间和功耗。

    Memory cell array biasing method and a semiconductor memory device
    35.
    发明申请
    Memory cell array biasing method and a semiconductor memory device 有权
    存储单元阵列偏置方法和半导体存储器件

    公开(公告)号：US20060164896A1

    公开(公告)日：2006-07-27

    申请号：US11327967

    申请日：2006-01-09

    申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

    摘要翻译： 提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。 半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到 多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

    Writing driver circuit of phase-change memory
    36.
    发明授权
    Writing driver circuit of phase-change memory 有权

    公开(公告)号：US07012834B2

    公开(公告)日：2006-03-14

    申请号：US10829807

    申请日：2004-04-22

    申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

    Data read circuit for use in a semiconductor memory and a method thereof
    37.
    发明申请
    Data read circuit for use in a semiconductor memory and a method thereof 有权
    用于半导体存储器的数据读取电路及其方法

    公开(公告)号：US20050030814A1

    公开(公告)日：2005-02-10

    申请号：US10943300

    申请日：2004-09-17

    申请人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

    发明人： Hyung-Rok Oh ,  Woo-Yeong Cho ,  Choong-Keun Kwak

    IPC分类号： G11C13/00 ,  G11C7/06 ,  G11C7/12 ,  G11C13/02 ,  G11C16/02 ,  G11C16/26 ,  H01L27/105 ,  H01L45/00 ,  G11C7/00

    CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0054 ,  G11C2207/005

    摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.

    摘要翻译： 提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。 该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿 在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

    Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same
    38.
    发明授权
    Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same 有权
    在写入操作中断期间操作非易失性存储器件的方法，非易失性存储器件，存储器和操作其的电子系统

    公开(公告)号：US08713408B2

    公开(公告)日：2014-04-29

    申请号：US13193191

    申请日：2011-07-28

    申请人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    发明人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1048

    摘要： A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

    摘要翻译： 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME
    39.
    发明申请
    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME 有权
    在写操作中断期间操作非易失性存储器件的方法，非易失性存储器件，存储器和操作其的电子系统

    公开(公告)号：US20120311407A1

    公开(公告)日：2012-12-06

    申请号：US13193191

    申请日：2011-07-28

    申请人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    发明人： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1048

    摘要： A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

    摘要翻译： 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。