公开(公告)号：US20100020617A1

公开(公告)日：2010-01-28

申请号：US12480352

申请日：2009-06-08

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/3454 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11551 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.

Abstract translation: 一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串 线条。 多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

公开(公告)号：US20090287879A1

公开(公告)日：2009-11-19

申请号：US12424135

申请日：2009-04-15

Applicant: Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

Inventor： Dong-Yean Oh ,  Woon-Kyung Lee ,  Seung-Chul Lee

IPC: G06F12/00 ,  G11C16/04 ,  G11C16/06 ,  G06F12/02

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.

Abstract translation: 集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。 每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。 可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。 存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

公开(公告)号：US20090230457A1

公开(公告)日：2009-09-17

申请号：US12381380

申请日：2009-03-11

Applicant: Jin-Sung Lee ,  Woon-Kyung Lee

Inventor： Jin-Sung Lee ,  Woon-Kyung Lee

IPC: H01L29/792 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

Abstract translation: 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US07579244B2

公开(公告)日：2009-08-25

申请号：US11455888

申请日：2006-06-20

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract translation: 本发明提供一种其中栅极与器件隔离膜自对准的半导体器件及其制造方法。 限制有源区的器件隔离膜设置在半导体衬底的一部分上，并且字线跨过器件隔离膜。 栅极图案设置在字线和有源区之间，并且隧道氧化膜设置在栅极图案和有源区之间。 栅极图案包括以相应顺序沉积的浮置栅极图案，栅极层间电介质膜图案和控制栅极电极图案，并且具有与器件隔离膜自对准的侧壁。 为了形成具有与器件隔离膜自对准的侧壁的栅极图案，在半导体衬底上分别形成栅极绝缘膜和栅极材料膜。

公开(公告)号：US20090140320A1

公开(公告)日：2009-06-04

申请号：US12275369

申请日：2008-11-21

Applicant: Seung-Jun LEE ,  Woon-Kyung LEE

Inventor： Seung-Jun LEE ,  Woon-Kyung LEE

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Abstract translation: 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US20080081413A1

公开(公告)日：2008-04-03

申请号：US11647671

申请日：2006-12-29

Applicant: Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

Inventor： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

Abstract translation: 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US20070190726A1

公开(公告)日：2007-08-16

申请号：US11699990

申请日：2007-01-31

Applicant: Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

Inventor： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11541

Abstract: Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

Abstract translation: 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US07057226B2

公开(公告)日：2006-06-06

申请号：US10170393

申请日：2002-06-14

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

公开(公告)号：US07015087B2

公开(公告)日：2006-03-21

申请号：US11029832

申请日：2005-01-04

Applicant: Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

Inventor： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

IPC: H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

公开(公告)号：US06448112B2

公开(公告)日：2002-09-10

申请号：US09791938

申请日：2001-02-23

Applicant: Woon-kyung Lee

Inventor： Woon-kyung Lee

IPC: H01L2182

CPC classification number: H01L27/11266 ,  G11C17/126 ,  H01L27/112 ,  Y10S257/908

Abstract: In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the plurality of word lines at right angles are formed. Trench regions are formed on the semiconductor substrate exposed by the plurality of word lines and the plurality of sub-bit lines. An interlayer insulating layer is formed on the entire surface of the resulting material, and a plurality of bit lines which are parallel to one another are formed on the interlayer insulating layer.

Abstract translation: 在NOR型掩模ROM器件的单元阵列区域及其制造方法中，在半导体衬底上形成彼此平行的多个字线之后，与多个栅极ROM器件的顶部相交的多个子位线 形成直角的字线。 在由多个字线和多个子位线露出的半导体衬底上形成沟槽区域。 在所得材料的整个表面上形成层间绝缘层，并且在层间绝缘层上形成彼此平行的多个位线。