公开(公告)号：US07192845B2

公开(公告)日：2007-03-20

申请号：US10864562

申请日：2004-06-08

Applicant: Yu Lin Yen ,  Ching-Yu Chang

Inventor： Yu Lin Yen ,  Ching-Yu Chang

IPC: H01L21/76 ,  H01L21/78 ,  H01L21/46 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

Abstract translation: 一种集成电路，其中后续层之间的对准测量对应力诱导偏移具有较小的敏感性。 该结构的第一层具有第一覆盖标记。 在对准结构中和第一层上形成第二层和/或第三层。 第二层和/或第三层的部分从第一重叠标记中和周围的区域选择性地去除。 形成第二重叠标记并与第一覆盖标记对准。 可以由于反射和折射或由于第一重叠标记的边缘轮廓偏移而具有衰减误差来测量第二覆盖标记和第一覆盖标记之间的对准。

公开(公告)号：US20070054197A1

公开(公告)日：2007-03-08

申请号：US11223480

申请日：2005-09-08

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32

Abstract: The present invention provides a mask comprising a substrate, a plurality of strip patterns and at least an assist pattern. The strip patterns are disposed on the substrate and arranged in parallel to one another. The assist pattern is in a strip shape and disposed on the substrate. The assist pattern is arranged in parallel to and outside of the outermost strip pattern of the strip patterns. The assist pattern and the strip pattern have the same phase, while the assist pattern has a width larger than that of the strip patterns. When the mask is applied for exposure process, the pattern of the assist pattern will not be transferred to the underlying layer to be exposed.

Abstract translation: 本发明提供了一种掩模，其包括基底，多个条状图案和至少一个辅助图案。 带状图案设置在基板上并且彼此平行地布置。 辅助图案为带状，并设置在基板上。 辅助图案平行于带状图案的最外面带状图案并排布置。 辅助图案和带状图案具有相同的相位，而辅助图案的宽度大于带状图案的宽度。 当掩模用于曝光处理时，辅助图案的图案将不会转移到要暴露的下层。

公开(公告)号：US20120112329A1

公开(公告)日：2012-05-10

申请号：US13350690

申请日：2012-01-13

Applicant: Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

Inventor： Yu-Lin YEN ,  Shih-Ming CHEN ,  Hsi-Chien LIN ,  Yu-Lung HUANG ,  Tsang-Yu LIU

IPC: H01L23/495

CPC classification number: H01L31/0203 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/048 ,  H01L2224/16 ,  H01L2924/1461 ,  Y02E10/50 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

Abstract translation: 本发明的一个实施例提供了一种芯片封装，其包括：半导体衬底，具有与器件区域相邻的器件区域和非器件区域; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域和所述非器件区域; 设置在所述半导体衬底和所述封装层之间以及所述间隔层和所述器件区域之间并围绕所述非器件区域的一部分的环形结构; 以及包括形成在间隔层或环结构中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。

公开(公告)号：US20110221070A1

公开(公告)日：2011-09-15

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

公开(公告)号：US07781126B2

公开(公告)日：2010-08-24

申请号：US11223480

申请日：2005-09-08

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32

Abstract: The present invention provides a mask comprising a substrate, a plurality of strip patterns and at least an assist pattern. The strip patterns are disposed on the substrate and arranged in parallel to one another. The assist pattern is in a strip shape and disposed on the substrate. The assist pattern is arranged in parallel to and outside of the outermost strip pattern of the strip patterns. The assist pattern and the strip pattern have the same phase, while the assist pattern has a width larger than that of the strip patterns. When the mask is applied for exposure process, the pattern of the assist pattern will not be transferred to the underlying layer to be exposed.

Abstract translation: 本发明提供了一种掩模，其包括基底，多个条状图案和至少一个辅助图案。 带状图案设置在基板上并且彼此平行地布置。 辅助图案为带状，并设置在基板上。 辅助图案平行于带状图案的最外面带状图案并排布置。 辅助图案和带状图案具有相同的相位，而辅助图案的宽度大于带状图案的宽度。 当掩模用于曝光处理时，辅助图案的图案将不会转移到要暴露的下层。

公开(公告)号：US07125741B2

公开(公告)日：2006-10-24

申请号：US10720735

申请日：2003-11-24

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/0276 ,  H01L21/0332 ,  Y10S438/952

Abstract: A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the first primer from the first DARC. After that, form a second DARC on the first DARC; form a second primer on the second DARC. Last, form a second patterned photo-resist layer on the second primer.

Abstract translation: 提供了图案化光刻胶层的返工工艺。 首先，在衬底上依次形成有第一DARC，第一底漆和第一图案化的光致抗蚀剂层。 接下来，从第一DARC去除第一图案化的光致抗蚀剂层和第一底漆。 之后，在第一个DARC上形成第二个DARC; 在第二个DARC上形成第二个引物。 最后，在第二底漆上形成第二图案的光致抗蚀剂层。

公开(公告)号：US07097921B2

公开(公告)日：2006-08-29

申请号：US10446927

申请日：2003-05-29

Applicant: Ching-Yu Chang ,  Yu-Lin Yen ,  Chin-Da Su

Inventor： Ching-Yu Chang ,  Yu-Lin Yen ,  Chin-Da Su

IPC: B32B18/00

CPC classification number: C23C28/00 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sandwich ARC structure for preventing metal to contact from shifting, the sandwich ARC structure comprising a first Ti layer formed on a metal laer and a first TiN layer formed on the first Ti layer. A second Ti layer is formed on the first TiN layer and a second TiN layer is formed on the second Ti layer. Wherein the sandwich ARC structure formed of first Ti/first TiN/second Ti/second TiN will reduces the tress between said metal layer and a dielectric layer formed below the metal layer.

Abstract translation: 一种用于防止金属接触移动的夹层ARC结构，所述夹层ARC结构包括形成在金属层上的第一Ti层和形成在第一Ti层上的第一TiN层。 在第一TiN层上形成第二Ti层，在第二Ti层上形成第二TiN层。 其中由第一Ti /第一TiN /第二Ti /第二TiN形成的夹层ARC结构将减少所述金属层和形成在金属层下面的电介质层之间的发束。

公开(公告)号：US20050236721A1

公开(公告)日：2005-10-27

申请号：US10833206

申请日：2004-04-26

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: G03F7/20 ,  G03F9/00 ,  H01L23/544

CPC classification number: G03F9/7003 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract translation: 公开了尽管轮廓偏移的能够运行的集成电路。 集成电路上的覆盖标记被沟槽包围，该沟槽倾向于减轻由施加到集成电路的应力引起的轮廓移位的影响。 因此，覆盖标记的位置倾向于不受应力的影响。

公开(公告)号：US20050009345A1

公开(公告)日：2005-01-13

申请号：US10720735

申请日：2003-11-24

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0276 ,  H01L21/0332 ,  Y10S438/952

Abstract: A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the first primer from the first DARC. After that, form a second DARC on the first DARC; form a second primer on the second DARC. Last, form a second patterned photo-resist layer on the second primer.

Abstract translation: 提供了图案化光刻胶层的返工工艺。 首先，在衬底上依次形成有第一DARC，第一底漆和第一图案化的光致抗蚀剂层。 接下来，从第一DARC去除第一图案化的光致抗蚀剂层和第一底漆。 之后，在第一个DARC上形成第二个DARC; 在第二个DARC上形成第二个引物。 最后，在第二底漆上形成第二图案的光致抗蚀剂层。