公开(公告)号：US08536671B2

公开(公告)日：2013-09-17

申请号：US13154337

申请日：2011-06-06

Applicant: Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

Inventor： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC: H01L31/0203

CPC classification number: H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。

公开(公告)号：US20070218410A1

公开(公告)日：2007-09-20

申请号：US11377159

申请日：2006-03-15

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03F7/26

CPC classification number: G03F7/091 ,  G03F7/095 ,  G03F7/168

Abstract: A method for forming a material layer with an anti-reflective layer as the top surface. The method comprises steps of providing a material layer and performing an ion implantation process to change a plurality of physical properties of a portion of the material layer near a top surface of the material layer so as to covert the portion of the material layer into an anti-reflective layer.

Abstract translation: 一种形成具有抗反射层作为顶表面的材料层的方法。 该方法包括以下步骤：提供材料层并执行离子注入工艺以改变材料层的顶表面附近的材料层的一部分的多个物理性能，以将材料层的该部分隐蔽成反层 反射层。

公开(公告)号：US06960411B2

公开(公告)日：2005-11-01

申请号：US10314959

申请日：2002-12-10

Applicant: Yu-Lin Yen ,  Ching-Yu Chang ,  Shun-Li Lin

Inventor： Yu-Lin Yen ,  Ching-Yu Chang ,  Shun-Li Lin

IPC: G03F1/00 ,  G03F1/36 ,  H01L21/762 ,  G03F9/00

CPC classification number: G03F1/36 ,  H01L21/76224

Abstract: A mask with extended mask window for forming patterns on a semiconductor substrate. The mask includes a main chip array having four sides for forming patterns of a main chip in a semiconductor substrate and a plurality of extended mask windows arranged around the main chip array. A method of dummy exposure using the mask includes providing a semiconductor substrate comprising a nitride layer with a plurality of main chip areas therein, and a plurality of unpatterned areas therein, forming a resist layer on the semiconductor substrate, providing an exposure mask comprising a main chip array and a plurality of extended mask windows, patterning the main chip areas of the semiconductor substrate using the main chip array of the exposure mask, patterning the unpatterned areas of the semiconductor substrate using the windows of the exposure mask, and removing the unexposed portions of the resist layer.

Abstract translation: 具有用于在半导体衬底上形成图案的扩展掩模窗口的掩模。 掩模包括具有用于形成半导体衬底中的主芯片的图案的四个侧面的主芯片阵列和布置在主芯片阵列周围的多个扩展掩模窗口。 使用掩模的伪曝光方法包括提供包括其中具有多个主芯片区域的氮化物层和其中多个未图案化区域的半导体衬底，在半导体衬底上形成抗蚀剂层，提供包括主体的曝光掩模 芯片阵列和多个扩展掩模窗口，使用曝光掩模的主芯片阵列图案化半导体衬底的主芯片区域，使用曝光掩模的窗口对半导体衬底的未图案化区域进行图案化，以及去除未曝光部分 的抗蚀剂层。

公开(公告)号：US20110221070A1

公开(公告)日：2011-09-15

申请号：US13044457

申请日：2011-03-09

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

公开(公告)号：US07781126B2

公开(公告)日：2010-08-24

申请号：US11223480

申请日：2005-09-08

Applicant: Yu-Lin Yen

Inventor： Yu-Lin Yen

IPC: G03F1/00

CPC classification number: G03F1/36 ,  G03F1/32

Abstract: The present invention provides a mask comprising a substrate, a plurality of strip patterns and at least an assist pattern. The strip patterns are disposed on the substrate and arranged in parallel to one another. The assist pattern is in a strip shape and disposed on the substrate. The assist pattern is arranged in parallel to and outside of the outermost strip pattern of the strip patterns. The assist pattern and the strip pattern have the same phase, while the assist pattern has a width larger than that of the strip patterns. When the mask is applied for exposure process, the pattern of the assist pattern will not be transferred to the underlying layer to be exposed.

Abstract translation: 本发明提供了一种掩模，其包括基底，多个条状图案和至少一个辅助图案。 带状图案设置在基板上并且彼此平行地布置。 辅助图案为带状，并设置在基板上。 辅助图案平行于带状图案的最外面带状图案并排布置。 辅助图案和带状图案具有相同的相位，而辅助图案的宽度大于带状图案的宽度。 当掩模用于曝光处理时，辅助图案的图案将不会转移到要暴露的下层。

公开(公告)号：US07125741B2

公开(公告)日：2006-10-24

申请号：US10720735

申请日：2003-11-24

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/0276 ,  H01L21/0332 ,  Y10S438/952

Abstract: A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the first primer from the first DARC. After that, form a second DARC on the first DARC; form a second primer on the second DARC. Last, form a second patterned photo-resist layer on the second primer.

Abstract translation: 提供了图案化光刻胶层的返工工艺。 首先，在衬底上依次形成有第一DARC，第一底漆和第一图案化的光致抗蚀剂层。 接下来，从第一DARC去除第一图案化的光致抗蚀剂层和第一底漆。 之后，在第一个DARC上形成第二个DARC; 在第二个DARC上形成第二个引物。 最后，在第二底漆上形成第二图案的光致抗蚀剂层。

公开(公告)号：US07097921B2

公开(公告)日：2006-08-29

申请号：US10446927

申请日：2003-05-29

Applicant: Ching-Yu Chang ,  Yu-Lin Yen ,  Chin-Da Su

Inventor： Ching-Yu Chang ,  Yu-Lin Yen ,  Chin-Da Su

IPC: B32B18/00

CPC classification number: C23C28/00 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sandwich ARC structure for preventing metal to contact from shifting, the sandwich ARC structure comprising a first Ti layer formed on a metal laer and a first TiN layer formed on the first Ti layer. A second Ti layer is formed on the first TiN layer and a second TiN layer is formed on the second Ti layer. Wherein the sandwich ARC structure formed of first Ti/first TiN/second Ti/second TiN will reduces the tress between said metal layer and a dielectric layer formed below the metal layer.

Abstract translation: 一种用于防止金属接触移动的夹层ARC结构，所述夹层ARC结构包括形成在金属层上的第一Ti层和形成在第一Ti层上的第一TiN层。 在第一TiN层上形成第二Ti层，在第二Ti层上形成第二TiN层。 其中由第一Ti /第一TiN /第二Ti /第二TiN形成的夹层ARC结构将减少所述金属层和形成在金属层下面的电介质层之间的发束。

公开(公告)号：US20050236721A1

公开(公告)日：2005-10-27

申请号：US10833206

申请日：2004-04-26

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: G03F7/20 ,  G03F9/00 ,  H01L23/544

CPC classification number: G03F9/7003 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract translation: 公开了尽管轮廓偏移的能够运行的集成电路。 集成电路上的覆盖标记被沟槽包围，该沟槽倾向于减轻由施加到集成电路的应力引起的轮廓移位的影响。 因此，覆盖标记的位置倾向于不受应力的影响。

公开(公告)号：US20050009345A1

公开(公告)日：2005-01-13

申请号：US10720735

申请日：2003-11-24

Applicant: Yu-Lin Yen ,  Ching-Yu Chang

Inventor： Yu-Lin Yen ,  Ching-Yu Chang

IPC: H01L21/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0276 ,  H01L21/0332 ,  Y10S438/952

Abstract: A rework process of patterned photo-resist layer is provided. First, a substrate is provided with a first DARC, a first primer and a first patterned photo-resist layer being sequentially formed thereon. Next, remove the first patterned photo-resist layer and the first primer from the first DARC. After that, form a second DARC on the first DARC; form a second primer on the second DARC. Last, form a second patterned photo-resist layer on the second primer.

Abstract translation: 提供了图案化光刻胶层的返工工艺。 首先，在衬底上依次形成有第一DARC，第一底漆和第一图案化的光致抗蚀剂层。 接下来，从第一DARC去除第一图案化的光致抗蚀剂层和第一底漆。 之后，在第一个DARC上形成第二个DARC; 在第二个DARC上形成第二个引物。 最后，在第二底漆上形成第二图案的光致抗蚀剂层。

公开(公告)号：US09136241B2

公开(公告)日：2015-09-15

申请号：US13446954

申请日：2012-04-13

Applicant: Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

Inventor： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/04 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Abstract translation: 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。