公开(公告)号：US20210117133A1

公开(公告)日：2021-04-22

申请号：US16658733

申请日：2019-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F3/06 ,  H03M7/30

Abstract: An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to an embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that are used to determine when data reduction has been completed.

公开(公告)号：US10802977B2

公开(公告)日：2020-10-13

申请号：US16218389

申请日：2018-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Georgios Mappouras ,  Amin Farmahini Farahani ,  Nuwan Jayasena

IPC: G06F12/08 ,  G06F12/0882 ,  G06F3/06

Abstract: A processing system tracks counts of accesses to memory pages using a set of counters located at the memory module that stores the pages, wherein the counts are adjusted at least in part based on refreshes of the memory pages. This approach allows a processing system to efficiently maintain the counts with relatively small counters and with relatively low overhead. Furthermore, the rate at which the counters are adjusted, relative to the page refreshes, is adjustable, so that the access counts are useful for a wide variety of application types.

公开(公告)号：US10310997B2

公开(公告)日：2019-06-04

申请号：US15273013

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F12/0802 ,  G06F13/16

Abstract: A processing system employs a memory module as a temporary write buffer to store write requests when a write buffer at a memory controller reaches a threshold capacity, and de-allocates the temporary write buffer when the write buffer capacity falls below the threshold. Upon receiving a write request, the memory controller stores the write request in a write buffer until the write request can be written to main memory. The memory controller can temporarily extend the memory controller's write buffer to the memory module, thereby accommodating temporary periods of high memory activity without requiring a large permanent write buffer at the memory controller.

公开(公告)号：US10133672B2

公开(公告)日：2018-11-20

申请号：US15267097

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paula Aguilera Diez ,  Amin Farmahini-Farahani ,  Nuwan Jayasena

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804

Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.

公开(公告)号：US20180239702A1

公开(公告)日：2018-08-23

申请号：US15440979

申请日：2017-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  Nuwan Jayasena

IPC: G06F12/0817 ,  G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0813 ,  G06F12/0811 ,  G06F12/0837 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1048

Abstract: A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.

公开(公告)号：US10049044B2

公开(公告)日：2018-08-14

申请号：US15181415

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Boyer ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/0804 ,  G06F12/0806 ,  G06F12/0842

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

公开(公告)号：US09947386B2

公开(公告)日：2018-04-17

申请号：US14492045

申请日：2014-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan Jayasena ,  Dong Ping Zhang

IPC: G11C11/4078 ,  G11C11/4096 ,  G11C5/02 ,  G11C7/04 ,  G11C8/12

CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/04 ,  G11C8/12

Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

公开(公告)号：US20180081590A1

公开(公告)日：2018-03-22

申请号：US15273013

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F12/0802 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F12/0802 ,  G06F2212/60 ,  Y02D10/14

Abstract: A processing system employs a memory module as a temporary write buffer to store write requests when a write buffer at a memory controller reaches a threshold capacity, and de-allocates the temporary write buffer when the write buffer capacity falls below the threshold. Upon receiving a write request, the memory controller stores the write request in a write buffer until the write request can be written to main memory. The memory controller can temporarily extend the memory controller's write buffer to the memory module, thereby accommodating temporary periods of high memory activity without requiring a large permanent write buffer at the memory controller.

公开(公告)号：US20180018104A1

公开(公告)日：2018-01-18

申请号：US15211488

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  Benjamin Y. Cho ,  Nuwan Jayasena

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0061 ,  G11C2013/0076

Abstract: Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. A write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells. The memory controller writes the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.

公开(公告)号：US20170293560A1

公开(公告)日：2017-10-12

申请号：US15268953

申请日：2016-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Nuwan Jayasena ,  Reena Panda ,  Onur Kayiran ,  Michael W. Boyer

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1016 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.