公开(公告)号：US09430421B2

公开(公告)日：2016-08-30

申请号：US14206236

申请日：2014-03-12

Applicant: ARM Limited

Inventor： Simon John Craske ,  Michael Alexander Kennedy ,  Andrew John Turner ,  Richard Anthony Lane

IPC: G06F13/26 ,  G06F13/38

CPC classification number: G06F13/26

Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.

Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。

公开(公告)号：US20240028235A1

公开(公告)日：2024-01-25

申请号：US17813396

申请日：2022-07-19

Applicant: ECS Partners Limited ,  Arm Limited

Inventor： Sulaiman Sadiq ,  Jonathon Hare ,  Geoffrey Merrett ,  Partha Prasun Maji ,  Simon John Craske

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0673

Abstract: Briefly, embodiments, such as methods and/or systems for employing external memory devices in the execution of activation function such as activation functions implemented in a neural network. In one aspect, a first activation input tensor may be partitioned as a plurality of tensor segments stored in one or more external memory devices. Individual stored tensor segments may be sequentially loaded to memories local to processing circuitry to apply activation functions associated with the stored tensor segments.

公开(公告)号：US11152076B2

公开(公告)日：2021-10-19

申请号：US16578754

申请日：2019-09-23

Applicant: Arm Limited

Inventor： Simon John Craske

IPC: G11C29/00 ,  G11C29/38 ,  G06F9/30

Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction. This provides a mechanism for allowing an apparatus to perform operations required by debug instructions in situations where the processing circuitry hardware is not able to natively perform those operations in response to the specified debug instruction.

公开(公告)号：US11074080B2

公开(公告)日：2021-07-27

申请号：US16864223

申请日：2020-05-01

Applicant: ARM Limited

Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

公开(公告)号：US10768938B2

公开(公告)日：2020-09-08

申请号：US16085053

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite ,  Simon John Craske ,  François Christopher Jacques Botman ,  Bradley John Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F9/34

Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.

公开(公告)号：US10552156B2

公开(公告)日：2020-02-04

申请号：US15497461

申请日：2017-04-26

Applicant: ARM Limited

Inventor： Simon John Craske

IPC: G06F9/38 ,  G06F9/30

Abstract: Processing circuitry for performing data processing operations includes issue control circuitry to control issue of the processing operations. Validity marking circuitry marks when input operands are valid and available within an issue queue, and is responsive to a first input operand of the plurality of input operands having a predetermined value to mark a second input operand of the plurality of input operands as meeting its validity condition (i.e. it is possible to determine from the first input operand that the result of the processing operation concerned will be independent of the value of the second input operand and accordingly there is no need to wait for it to actually be available). In order to resolve ordering constraint problems which may be associated with the use of the early valid marking technique separate ordering valid flags may be provided and monitored in respect of at least order-constrained processing operations.

公开(公告)号：US20190286831A1

公开(公告)日：2019-09-19

申请号：US16433296

申请日：2019-06-06

Applicant: ARM Limited

Inventor： Simon John Craske ,  Antony John Penton

IPC: G06F21/62 ,  G06F13/24 ,  G06F9/48 ,  G06F21/50 ,  G06F9/30 ,  G06F9/455 ,  G06F21/60

Abstract: A data processing apparatus has processing circuitry for executing first software at a first privilege level and second software at a second privilege level higher than the first privilege level. Attributes may be set by the first and second software to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software specifies that the execution of the instruction cannot be interrupted.

公开(公告)号：US10102160B2

公开(公告)日：2018-10-16

申请号：US14581290

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Michael Kennedy ,  Simon John Craske ,  Andrew Turner ,  Richard Anthony Lane

IPC: G06F13/32 ,  G06F13/16

Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

公开(公告)号：US10073620B2

公开(公告)日：2018-09-11

申请号：US14926249

申请日：2015-10-29

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F17/00 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/10 ,  G06F12/14

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/10 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1016 ,  G06F2212/60

Abstract: Memory management is provided within a data processing system 2 which includes a memory protection unit 8 and defines memory regions within the memory address space which extend between base addresses and limit addresses and have respective attributes associated therewith. When a hit occurs within a memory region which is a valid hit, then block data is generated comprising a mask value and a TAG value (derived from the original query address) which may then be used to identify subsequent hits within at least a portion of that region using a bitwise AND. In another embodiment a micro-translation lookaside buffer is reused by the memory protection unit to store page data identifying pages which fall validly within memory regions and may be used to return attribute data for those pages upon subsequent accesses rather than performing the comparison with the base address and the limit addresses.

公开(公告)号：US09213828B2

公开(公告)日：2015-12-15

申请号：US13680352

申请日：2012-11-19

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite ,  Simon John Craske

IPC: G06F21/00 ,  G06F21/52 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F21/52 ,  G06F9/30134 ,  G06F9/462 ,  G06F2221/034 ,  G06F2221/2105

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.

Abstract translation: 数据处理装置包括处理电路和数据存储器，其包括包括安全区域和较不安全区域的多个区域。 安全区域被配置为存储当在安全域中操作时电路可访问的敏感数据，并且当在较不安全的域中操作时不被电路访问。 数据存储器包括在安全区域中具有安全堆栈的多个堆叠。 堆栈访问电路被配置为将预定的处理状态存储到安全堆栈。 处理电路还包括故障检查电路，其被配置为如果存储在预定相对位置中的数据是第一值，则识别第一故障状况。 这提供了防止来自较不安全的域的攻击的保护，例如执行从异常返回的函数调用或来自函数调用的异常返回。