公开(公告)号：US20240220296A1

公开(公告)日：2024-07-04

申请号：US18090605

申请日：2022-12-29

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： Philip Ng ,  Nippon Raval ,  Jeremy W. Powell ,  Donald Matthews, JR. ,  David Kaplan

IPC: G06F9/455 ,  G06F12/1081

CPC classification number: G06F9/45558 ,  G06F12/1081 ,  G06F2009/45587

Abstract: A processor manages memory-mapped input/output (MMIO) accesses, in secure fashion, at an input/output memory management unit (IOMMU). The processor is configured to ensure that, for a given MMIO request issued by a processor core and associated with a particular executing VM, the request is targeted to a MMIO address that has been assigned to the VM by a security module (e.g., a security co-processor). The processor thus prevents a malicious entity from accessing confidential information of a VM via MMIO requests.

公开(公告)号：US20240202015A1

公开(公告)日：2024-06-20

申请号：US18066155

申请日：2022-12-14

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Lu Lu ,  Anthony Asaro ,  Gia Tung Phan ,  Gongxian Cheng ,  Philip Ng ,  Yinan Jiang ,  Felix Kuehling

IPC: G06F9/455 ,  G06F9/54

CPC classification number: G06F9/45545 ,  G06F9/45558 ,  G06F9/545 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: In a computing device, a hardware device (e.g., a parallel accelerated processor or graphics processing unit) is coupled to a bus, such as a peripheral component interconnect express (PCIe) bus. The hardware device supports physical partitioning that allows physical resources of the hardware device to be separated into different partitions. Examples of such physical resources include engine resources (e.g., compute resources, direct memory access resources), memory resources (e.g., random access memory), and so forth. Each physical partition is mapped to a physical function that is exposed to a host on the computing device in a manner that is compliant with the bus protocol, allowing software to access the physical partition in a conventional manner based on the bus protocol.

公开(公告)号：US20240111688A1

公开(公告)日：2024-04-04

申请号：US17957742

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Omar Fakhri Ahmed ,  Norman Vernon Douglas Stewart ,  Mihir Shaileshbhai Doctor ,  Jason Todd Arbaugh ,  Milind Baburao Kamble ,  Philip Ng ,  Xiaojian Liu

IPC: G06F12/109

CPC classification number: G06F12/109 ,  G06F2212/657

Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.

公开(公告)号：US20210192087A1

公开(公告)日：2021-06-24

申请号：US16721895

申请日：2019-12-19

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Guhan Krishnan ,  Carl K. Wakeland ,  Saikishore Reddipalli ,  Philip Ng

IPC: G06F21/74 ,  H04L29/08 ,  G06F21/57 ,  G06F13/42 ,  G06F15/78

Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.

公开(公告)号：US11042495B2

公开(公告)日：2021-06-22

申请号：US16578165

申请日：2019-09-20

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F13/24 ,  G06F9/455 ,  G06F13/16

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

公开(公告)号：US10824349B1

公开(公告)日：2020-11-03

申请号：US16222334

申请日：2018-12-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Maggie Chan ,  Philip Ng ,  David Kaplan

IPC: G06F3/06 ,  G06F21/60 ,  G06F9/455 ,  H04L9/06

Abstract: A processing system includes a plurality of input/output (I/O) devices representing a plurality of I/O resources. Each I/O resource has at least one corresponding memory mapped I/O (MMIO) address range. A trap handler detects a write request targeting a configuration space of an identified I/O resource of the plurality of I/O resources and, responsive to determining the identified I/O resource is a protected I/O resource, selectively blocks the write request from further processing by the processing system based on whether the write request would change an MMIO address decoding of the identified I/O resource.

公开(公告)号：US20200226081A1

公开(公告)日：2020-07-16

申请号：US16249649

申请日：2019-01-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Alexander J. Branover ,  Kevin M. Lepak

IPC: G06F13/16 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

公开(公告)号：US20150106916A1

公开(公告)日：2015-04-16

申请号：US14052182

申请日：2013-10-11

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： David A. Kaplan ,  Philip Ng

IPC: G06F21/85 ,  G06F3/00

CPC classification number: G06F9/4411 ,  G06F9/30145 ,  G06F9/3881

Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.

Abstract translation: 一种方法包括在处理器的处理单元中执行微代码以实现机器指令，其中微代码是操纵处理单元以公共通信总线上的外部设备访问公用通信上的其他设备不可见的专用地址 总线，并未在机器指令中指定。 处理器包括公共通信总线，耦合到公共通信总线的外围设备和处理单元。 处理单元是执行微代码来实现机器指令。 微代码是操纵处理单元以公用通信总线上的公共通信总线上的外部设备访问公共通信总线上的其他设备不可见的私有地址，并且未在机器指令中指定。

公开(公告)号：US10909053B2

公开(公告)日：2021-02-02

申请号：US16423077

申请日：2019-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F9/455 ,  G06F12/1009 ,  G06F12/02 ,  G06F12/0875 ,  G06F13/16

Abstract: An electronic device includes a processor that executes a guest operating system, an input-output memory management unit (IOMMU), and a main memory that stores an IOMMU backing store. The IOMMU backing store includes a separate copy of a set of IOMMU memory-mapped input-output (MMIO) registers for each guest operating system in a set of supported guest operating systems. The IOMMU receives, from the guest operating system, a communication that accesses data in a given IOMMU MMIO register. The IOMMU then performs a corresponding access of the data in a copy of the given IOMMU MMIO register in the IOMMU backing store associated with the guest operating system.

公开(公告)号：US11494211B2

公开(公告)日：2022-11-08

申请号：US16390663

申请日：2019-04-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F9/455 ,  G06F12/1009

Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.