公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20240112747A1

公开(公告)日：2024-04-04

申请号：US17957808

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Tahsin Askar ,  Naveen Davanam ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C29/10

CPC classification number: G11C29/10

Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.

公开(公告)号：US20240112722A1

公开(公告)日：2024-04-04

申请号：US17957820

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  James R. Magro ,  Kedarnath Balakrishnan ,  Jing Wang

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40622

Abstract: A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.

公开(公告)号：US20240005971A1

公开(公告)日：2024-01-04

申请号：US17853418

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/109

Abstract: An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.

公开(公告)号：US20230368832A1

公开(公告)日：2023-11-16

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G11C11/406 ,  G06F9/4401 ,  G06F1/3203

CPC classification number: G11C11/40611 ,  G06F9/442 ,  G06F1/3203 ,  G11C11/40615 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11797369B2

公开(公告)日：2023-10-24

申请号：US17864804

申请日：2022-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F11/0772 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/141

Abstract: A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

公开(公告)号：US11669274B2

公开(公告)日：2023-06-06

申请号：US17218676

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a dynamic random access memory (DRAM) memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and the associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for a bank group of the prior write request.

公开(公告)号：US11664062B2

公开(公告)日：2023-05-30

申请号：US16938855

申请日：2020-07-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/00 ,  G11C11/406 ,  G06F9/4401 ,  G06F1/3203

CPC classification number: G11C11/40611 ,  G06F1/3203 ,  G06F9/442 ,  G11C11/40615 ,  G06F9/4401

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US11494316B2

公开(公告)日：2022-11-08

申请号：US17085304

申请日：2020-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Brendan T. Mangan

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G06F12/1009

Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

公开(公告)号：US20220122652A1

公开(公告)日：2022-04-21

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.