公开(公告)号：US20180088858A1

公开(公告)日：2018-03-29

申请号：US15274777

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US20170337136A1

公开(公告)日：2017-11-23

申请号：US15162464

申请日：2016-05-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Bradford M. Beckmann ,  Shuai Che ,  Sooraj Puthoor

IPC: G06F12/1009 ,  G06F12/0815 ,  G06F12/14

CPC classification number: G06F12/1009 ,  G06F12/0817 ,  G06F12/0837 ,  G06F12/1027 ,  G06F12/1483 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/621 ,  G06F2212/657

Abstract: The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device sets a cache coherency indicator in metadata in a page table entry in a page table, the page table entry information about a page of data that is stored in the memory. The computing device then uses the cache coherency indicator to determine operations to be performed when accessing data in the page of data in the memory. For example, the computing device can use the coherency indicator to determine whether a coherency operation is to be performed when a processor of a given type accesses data in the page of data in the memory.

公开(公告)号：US20160371082A1

公开(公告)日：2016-12-22

申请号：US14746601

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  Arkaprava Basu ,  Sooraj Puthoor ,  Joseph L. Greathouse

IPC: G06F9/30

CPC classification number: G06F9/461 ,  G06F9/3013 ,  G06F9/3851

Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.

Abstract translation: 处理装置包括包括上下文缓冲器的第一存储器。 处理设备还包括处理器核心，用于基于存储在处理器核心的寄存器中的上下文信息来执行线程，以及存储器控制器，用于基于上下文缓冲器和寄存器的一个或多个延迟来选择性地移动上下文信息的子集 线程。

公开(公告)号：US20240419330A1

公开(公告)日：2024-12-19

申请号：US18211544

申请日：2023-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Sooraj Puthoor

IPC: G06F3/06

Abstract: Scheduling processing-in-memory transactions in systems with multiple memory controllers is described. In accordance with the described techniques, an addressing system segments operations of a transaction into multiple microtransactions, where each microtransaction includes a subset of the transaction operations that are scheduled by a corresponding one of the multiple memory controllers. Each transaction, and its associated microtransactions, is assigned a transaction identifier based on a current counter value maintained at the multiple memory controllers, and the multiple memory controllers schedule execution of microtransactions based on associated transaction identifiers to ensure atomic execution of operations for a transaction without interruption by operations of a different transaction.

公开(公告)号：US20240220265A1

公开(公告)日：2024-07-04

申请号：US18147103

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Nuwan S. Jayasena

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/3836 ,  G06F9/4806 ,  G06F9/5061

Abstract: Resource access control is described. In accordance with the described techniques, a process (e.g., an application process, a system process, etc.) issues an instruction seeking access to a computation resource (e.g., a processor resource, a memory resource, etc.) to perform a computation task. An execution context for the instruction is checked to determine whether the execution context includes a resource indicator indicating permission to access the processor resource. Alternatively or additionally, the instruction is checked against an access table which identifies processes that are permitted and/or not permitted to access the computation resource.

公开(公告)号：US12019560B2

公开(公告)日：2024-06-25

申请号：US17556431

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/1072 ,  G06F13/16

CPC classification number: G06F12/1072 ,  G06F12/0238 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1673 ,  G06F2212/7201

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

公开(公告)号：US20240111591A1

公开(公告)日：2024-04-04

申请号：US17957907

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Michael Beckmann ,  Sooraj Puthoor

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5038 ,  G06F9/3009 ,  G06F9/5072

Abstract: Portions of programs, oftentimes referred to as kernels, are written by programmers to target a particular type of compute unit, such as a central processing unit (CPU) core or a graphics processing unit (GPU) core. When executing a kernel, the kernel is separated into multiple parts referred to as workgroups, and each workgroup is provided to a compute unit for execution. Usage of one type of compute unit is monitored and, in response to the one type of compute unit being idle, one or more workgroups targeting another type of compute unit are executed on the one type of compute unit. For example, usage of CPU cores is monitored, and in response to the CPU cores being idle, one or more workgroups targeting GPU cores are executed on the CPU cores.

公开(公告)号：US11934698B2

公开(公告)日：2024-03-19

申请号：US17556503

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F7/575

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0679 ,  G06F7/575

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

公开(公告)号：US11734059B2

公开(公告)日：2023-08-22

申请号：US16824601

申请日：2020-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber Hassaan ,  Anirudh Mohan Kaushik ,  Sooraj Puthoor ,  Gokul Subramanian Ravi ,  Bradford Beckmann ,  Ashwin Aji

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F16/9024 ,  G06F2209/486

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US20230196502A1

公开(公告)日：2023-06-22

申请号：US18103322

申请日：2023-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Muhammad Amber Hassaan ,  Sooraj Puthoor

IPC: G06T1/60 ,  G06F9/30 ,  G06F12/02 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/30098 ,  G06F12/023 ,  G06T1/20 ,  G06F12/02

Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.