公开(公告)号：US07205185B2

公开(公告)日：2007-04-17

申请号：US10663471

申请日：2003-09-15

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Kathryn W. Guarini ,  Suryanarayan G. Hegde ,  MeiKei Ieong ,  Erin Catherine Jones

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

公开(公告)号：US07198995B2

公开(公告)日：2007-04-03

申请号：US10733378

申请日：2003-12-12

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。

公开(公告)号：US07037770B2

公开(公告)日：2006-05-02

申请号：US10687608

申请日：2003-10-20

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在nFET沟道的沟道中生长SiGe层，并且在pFET沟道中生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配，以在覆盖的生长的外延层中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在另一实施方案中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：US07026247B2

公开(公告)日：2006-04-11

申请号：US10696686

申请日：2003-10-28

申请人： Omer H. Dokumaci ,  Oleg Gluschenkov

发明人： Omer H. Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L21/461

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/82385 ,  Y10S438/947

摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.

摘要翻译： 提供了用于制造微结构的自校正蚀刻（SCORE）工艺。 本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。 或者，通过应用SCORE可以显着地减少在打印期间产生的硬掩模特征的CD变化。 因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。 因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。

公开(公告)号：US06872641B1

公开(公告)日：2005-03-29

申请号：US10667603

申请日：2003-09-23

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/205 ,  C30B1/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/322 ,  H01L21/324 ,  H01L21/36 ,  H01L29/10

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/1054

摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained layer. During the annealing, interstitial dislocation loops are formed as uniformly tributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。

公开(公告)号：US06806534B2

公开(公告)日：2004-10-19

申请号：US10342423

申请日：2003-01-14

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66553

摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

公开(公告)号：US06803315B2

公开(公告)日：2004-10-12

申请号：US10212938

申请日：2002-08-05

申请人： Omer H. Dokumaci ,  Bruce B. Doris

发明人： Omer H. Dokumaci ,  Bruce B. Doris

IPC分类号： H01L21302

CPC分类号： H01L29/66545 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.

摘要翻译： 提供了一种用于阻挡来自FET器件的栅电极的植入物的方法。 形成覆盖基板和栅极电极堆叠的第一平坦化膜。 第一平面化膜通过抛光或自平面平坦化。 为了通过HDP沉积或者在材料上使用旋涂，该膜是自平面化的。 在需要抛光的情况下，第一平面化膜通过抛光进行平坦化，直到栅电极的顶部露出。 在第一平面化膜的上表面的水平面下方蚀刻栅电极。 然后沉积第二平坦化膜和抛光剂的覆盖层以将其平坦化至暴露第一平坦化膜的水平，将第二平坦化膜形成为覆盖栅极顶表面的注入块。 取下第一个平面化膜。 通过使用注入块将掺杂剂注入衬底来形成反向掺杂区域，以阻止掺杂剂注入到栅电极中。 注入块在植入反向掺杂区域期间保护FET的栅电极免受不希望的注入杂质。 第一平面化膜由选自HDP（高密度等离子体）氧化硅和HDP氮化硅的材料，包含ONO的层间介电层材料和光致抗蚀剂组成。 栅电极由选自多晶硅和金属的材料组成。 第二平面化膜包括诸如HDP氧化物，HDP氮化物和包括ARC的有机层的材料。 第二平面化膜包括与第一平坦化膜不同的材料。

公开(公告)号：US06569781B1

公开(公告)日：2003-05-27

申请号：US10054078

申请日：2002-01-22

申请人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

发明人： Omer H. Dokumaci ,  Richard D. Kaplan ,  Mukesh V. Khare ,  Suryanarayan G. Hegde

IPC分类号： H01L21265

CPC分类号： H01L21/28211 ,  H01L21/26506 ,  H01L21/2822 ,  H01L21/28238 ,  H01L29/518

摘要： A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

摘要翻译： 在硅衬底上形成氧化物层的方法包括在硅衬底上形成牺牲氧化物层，将氮注入到硅衬底中，退火具有注入氮的硅衬底，从硅衬底去除牺牲氧化层， 硅衬底上的氧化物层。 植入硅中的氮的剂量优选高于1e14cm31 2.退火过程优选在约550℃至约1000℃的温度下进行约1秒至约2秒的时间 小时。

公开(公告)号：US08633071B2

公开(公告)日：2014-01-21

申请号：US13278667

申请日：2011-10-21

申请人： Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

发明人： Duresti Chidambarrao ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov

IPC分类号： H01L21/8238

CPC分类号： H01L29/1608 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/66651 ,  H01L29/7378 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/8086

摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

公开(公告)号：US07964865B2

公开(公告)日：2011-06-21

申请号：US11048739

申请日：2005-02-03

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L29/06

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/1054

摘要： A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

摘要翻译： 提供一种形成半导体衬底结构的方法。 在硅衬底上形成压缩应变SiGe层。 原子被离子注入SiGe层以造成范围内的损伤。 进行退火以松弛应变的SiGe层。 在退火过程中，间隙位错环形成均匀分布在SiGe层中。 间隙位错环为SiGe层和硅衬底之间的失配位错的成核提供了基础。 由于间隙位错环分布均匀，因此错位位置也均匀分布，从而松弛SiGe层。 在松弛的SiGe层上形成拉伸应变硅层。