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公开(公告)号：US06893951B2
公开(公告)日：2005-05-17
申请号：US10848759
申请日：2004-05-18
IPC分类号： G11C5/00 , G11C17/16 , H01L23/525 , H01L21/44 , H01L21/3205 , H01L21/8234
CPC分类号： G11C5/063 , G11C5/02 , G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Interconnection structures for integrated circuits have first cells disposed in a first plane, at least second cells disposed in at least a second plane parallel to the first plane, and vertical interconnections disposed for connecting conductors in the first plane with conductors in the second plane, at least some of the vertical interconnections initially incorporating antifuses. The antifuses may be disposed over conductors that are disposed on a base substrate. The antifuses are selectively fused to prepare the integrated circuit for normal operation. Methods for fabricating and using such vertical interconnection structures are disclosed.
摘要翻译： 用于集成电路的互连结构具有设置在第一平面中的第一单元，至少第二单元设置在平行于第一平面的至少第二平面中，并且垂直互连设置用于将第一平面中的导体与第二平面中的导体连接， 最初的一些垂直互连最初包含反熔丝。 反熔丝可以设置在设置在基底基板上的导体上。 反熔丝被选择性地熔合以制备用于正常操作的集成电路。 公开了用于制造和使用这种垂直互连结构的方法。
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公开(公告)号：US06879525B2
公开(公告)日：2005-04-12
申请号：US10001680
申请日：2001-10-31
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/009 , G11C2213/72
摘要： An integrated circuit includes an array of state-change devices, first and second decoder circuits for selecting a particular state-change device. A voltage source is coupled to the first decoder circuit and sense circuitry is coupled to the second decoder to receive an electrical parameter from the selected state-change device and to detect a particular value of the electrical parameter. A control circuit is coupled to the voltage source, the first and second decoders, and the sense circuitry to select a first voltage from the voltage source to alter the selected state-change device and to select a second voltage from the voltage source when the sense circuitry detects the particular value of the electrical parameter.
摘要翻译： 集成电路包括状态变换器件阵列，用于选择特定状态改变器件的第一和第二解码器电路。 电压源耦合到第一解码器电路，并且感测电路耦合到第二解码器以从所选择的状态改变装置接收电参数并且检测电参数的特定值。 控制电路耦合到电压源，第一和第二解码器以及感测电路，以从电压源选择第一电压以改变所选择的状态改变装置，并且当感测时选择来自电压源的第二电压 电路检测电参数的特定值。
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公开(公告)号：US20050021824A1
公开(公告)日：2005-01-27
申请号：US10617001
申请日：2003-07-09
申请人： Daryl Anderson , Peter Fricke , Andy Brocklin
发明人： Daryl Anderson , Peter Fricke , Andy Brocklin
CPC分类号： H04N1/00281 , H04L51/04 , H04M3/567 , H04M11/06 , H04N1/00302 , H04N1/00392
摘要： Disclosed are systems and methods for transmitting graphical data via a communication line. For example, in one embodiment, a system includes means for receiving voice data, means for generating graphical data representative of a user input, and means for simultaneously transmitting the voice data and information representative of the generated graphical data via a communication line such that a bandwidth of the communication line is not exceeded.
摘要翻译： 公开了用于经由通信线路发送图形数据的系统和方法。 例如，在一个实施例中，系统包括用于接收语音数据的装置，用于产生表示用户输入的图形数据的装置，以及用于经由通信线路同时发送表示所生成的图形数据的语音数据和信息的装置， 不超过通信线路的带宽。
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公开(公告)号：US06831861B2
公开(公告)日：2004-12-14
申请号：US10756450
申请日：2004-01-12
IPC分类号： G11C700
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.
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公开(公告)号：US06774458B2
公开(公告)日：2004-08-10
申请号：US10202105
申请日：2002-07-23
IPC分类号： H01L2900
CPC分类号： G11C5/063 , G11C5/02 , G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Interconnection structures for integrated circuits have first cells disposed in a first plane, at least second cells disposed in at least a second plane parallel to the first plane, and vertical interconnections disposed for connecting conductors in the first plane with conductors in the second plane, at least some of the vertical interconnections initially incorporating antifuses. The antifuses may be disposed over conductors that are disposed on a base substrate. The antifuses are selectively fused to prepare the integrated circuit for normal operation. Methods for fabricating and using such vertical interconnection structures are disclosed.
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公开(公告)号：US06687147B2
公开(公告)日：2004-02-03
申请号：US10202174
申请日：2002-07-23
IPC分类号： G11C506
CPC分类号： H01L27/0688 , G11C5/025 , G11C7/18 , H01L21/8221 , H01L27/105 , H01L27/1052
摘要： A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
摘要翻译： 一种创建存储器电路的方法优选地包括：（1）在基本上平行于衬底的平面中形成第一组多个选择线，（2）在基本上平行于衬底的平面中形成第二组选择线，其中 第二组选择线被分成第一组和第二组，其中第一组形成在与第一组多个选择线的方向垂直的方向上，并且第二组形成在与第一组大致对角线的方向上 第一组，（3）形成与衬底垂直的多个支柱，以及（4）形成存储器单元的阵列，每个存储单元分别耦合到一个柱和每个所述第一和第二多个选择线中的一个 。
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公开(公告)号：US06677220B2
公开(公告)日：2004-01-13
申请号：US10386597
申请日：2003-03-12
IPC分类号： H01L21326
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.
摘要翻译： 反熔丝结构在第一和第二导热区域之间具有反熔丝。 第一和第二导热区域中的每一个具有低热导率的部分和高导热率的一部分。 具有低热导率的部分在高热导率的相应部分和反熔丝之间。
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公开(公告)号：US06661691B2
公开(公告)日：2003-12-09
申请号：US10115763
申请日：2002-04-02
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L23/522 , H01L27/112 , H01L2924/0002 , Y10S977/789 , Y10S977/801 , Y10S977/906 , Y10S977/943 , H01L2924/00
摘要： Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.
摘要翻译： 用于集成电路的互连结构具有第一阵列阵列，平行于第一阵列的至少第二阵列阵列，以及布置用于将第一阵列的单元与第二阵列的单元相连接的互连，至少部分布线被布置 沿着与第一和第二阵列倾斜定向的轴。 互连的第一组和第二组倾斜轴线可以彼此平行或相对。 互连可以包括倾斜的立柱或沿斜轴设置的阶梯式柱。 公开了制造和使用这种结构的方法。
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39.发明授权Defective memory component of a memory device used to represent a data bit in a bit sequence 有权用于表示位序列中的数据位的存储器件的存储器组件有缺陷公开(公告)号：US06570795B1
公开(公告)日：2003-05-27
申请号：US10120473
申请日：2002-04-10
IPC分类号： G11C700
摘要： A memory device includes memory components that represent a logic value corresponding to a data bit in a bit sequence. A defective memory component in the memory device represents a data bit in the bit sequence. An additional memory component in the memory device represents an encode bit in the bit sequence, where the encode bit indicates whether the bit sequence is inverted.
摘要翻译： 存储器件包括表示与位序列中的数据位对应的逻辑值的存储器组件。 存储器件中的缺陷存储器部件表示位序列中的数据位。 存储器件中的附加存储器组件表示位序列中的编码位，其中编码位指示位序列是否被反转。
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公开(公告)号：US20100045582A1
公开(公告)日：2010-02-25
申请号：US12374977
申请日：2007-07-19
申请人： Peter Fricke , Alan R. Arthur , Joseph Stellbrink , Tim R. Koch
发明人： Peter Fricke , Alan R. Arthur , Joseph Stellbrink , Tim R. Koch
IPC分类号： G09G3/36
CPC分类号： G09G3/364 , G02F1/133371 , G02F1/1391 , G02F2001/134345 , G09G3/3637
摘要： A display element (100) corresponds to a pixel of a display. The display element includes a top electrode (102) connected to a first addressable line of the display, and a bottom electrode (104) connected to a second addressable line of the display. The display element includes a display mechanism (106) situated between the top electrode and the bottom electrode and having a number of individually turned-on steps. Each individually turned-on step has a turn-on voltage threshold at which the step is turned on upon a voltage applied between the top and the bottom electrodes equal to or greater than the turn-on voltage threshold. Each individually turned-on step has a turn-off voltage threshold at which the step is turned off upon a voltage applied between the top and the bottom electrodes equal to or less than the turn-off voltage threshold.
摘要翻译： 显示元件（100）对应于显示器的像素。 显示元件包括连接到显示器的第一可寻址线路的顶部电极（102）和连接到显示器的第二可寻址线路的底部电极（104）。 显示元件包括位于顶部电极和底部电极之间并具有多个单独接通步骤的显示机构（106）。 每个单独导通步骤具有接通电压阈值，在施加在顶部电极和底部电极之间的电压等于或大于导通电压阈值时，该步骤被接通。 每个单独导通步骤具有截止电压阈值，在该阈值处，在施加在顶部和底部电极之间的电压等于或小于关断电压阈值时，该步骤被关断。
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