公开(公告)号：US20070187800A1

公开(公告)日：2007-08-16

申请号：US11737304

申请日：2007-04-19

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01C17/267

摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

公开(公告)号：US20050233478A1

公开(公告)日：2005-10-20

申请号：US10709109

申请日：2004-04-14

申请人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L23/525 ,  H01L27/08 ,  H01P3/08

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US20060166454A1

公开(公告)日：2006-07-27

申请号：US10905940

申请日：2005-01-27

申请人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

发明人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/26513 ,  H01L27/0802 ,  H01L28/20

摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

摘要翻译： 提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。 在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。 激活可以通过沉积保护性介电层或单独的激活退火来进行。 在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

公开(公告)号：US20080018378A1

公开(公告)日：2008-01-24

申请号：US11865432

申请日：2007-10-01

申请人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Hayden Cranford ,  Terence Hook ,  Anthony Stamper

IPC分类号： H03H7/00

CPC分类号： H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US20060152333A1

公开(公告)日：2006-07-13

申请号：US10905546

申请日：2005-01-10

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Terence Hook ,  Robert Rassel ,  Edmund Sprogis ,  Anthony Stamper ,  William Murphy

IPC分类号： H01C1/08

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US20070275534A1

公开(公告)日：2007-11-29

申请号：US11839106

申请日：2007-08-15

申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

IPC分类号： H01L21/331

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US20070105354A1

公开(公告)日：2007-05-10

申请号：US11164108

申请日：2005-11-10

申请人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L21/425

CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

公开(公告)号：US20050093053A1

公开(公告)日：2005-05-05

申请号：US11001140

申请日：2004-12-02

申请人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

发明人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

IPC分类号： H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08 ,  H01L31/11

CPC分类号： H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

公开(公告)号：US20050054171A1

公开(公告)日：2005-03-10

申请号：US10953378

申请日：2004-09-29

申请人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

发明人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US20070254449A1

公开(公告)日：2007-11-01

申请号：US11627408

申请日：2007-01-26

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Richard Rassel ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Richard Rassel ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L28/20

摘要： Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

摘要翻译： 整合在集成电路中的可调TCR电阻和制造可调TCR电阻的方法。 可调TCR电阻器包括具有相反极性和不同幅度TCR，相同极性和不同幅度TCR或具有相反极性和大约相同TCR的两种或更多种不同材料的两个或更多个电阻器。