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    Method and system for forming dual work function gate electrodes in a semiconductor device
    32.
    发明授权
    Method and system for forming dual work function gate electrodes in a semiconductor device 有权
    在半导体器件中形成双功函数栅电极的方法和系统

    公开(公告)号：US06794252B2

    公开(公告)日：2004-09-21

    申请号：US10254396

    申请日：2002-09-25

    申请人： Antonio L. P. Rotondaro ,  Mark R. Visokay

    发明人： Antonio L. P. Rotondaro ,  Mark R. Visokay

    IPC分类号： H01L218234

    CPC分类号： H01L21/28194 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/51 ,  H01L29/518

    摘要： A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

    摘要翻译： 提供了一种用于形成双功函数栅电极的方法。 介电层设置在基板的外侧。 在电介质层的外侧形成金属层。 在金属层的外部形成硅锗层。 去除硅 - 锗层的第一部分以暴露金属层的第一部分，硅 - 锗层的第二部分保留在金属层的第二部分上。 硅 - 锗金属化合物层由硅 - 锗层的第二部分和金属层的第二部分形成。 形成包括金属层的第一部分的第一栅电极。 形成包含硅 - 锗金属化合物层的第二栅电极。

    Ultra-thin SiO2using N2O as the oxidant
    34.
    发明授权
    Ultra-thin SiO2using N2O as the oxidant 有权
    使用N2O作为氧化剂的超薄SiO2

    公开(公告)号：US06638877B2

    公开(公告)日：2003-10-28

    申请号：US09971385

    申请日：2001-10-04

    申请人： Antonio L. P. Rotondaro

    发明人： Antonio L. P. Rotondaro

    IPC分类号： H01L2131

    CPC分类号： H01L21/28211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/31658 ,  H01L21/31662 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

    摘要： N2O is used as the oxidant for forming an ultra-thin oxide (14). The low oxidation efficiency of N2O compared to O2 allows the oxidation temperature to be raised to greater than 850° C. while maintaining the growth rate. A cold wall lamp heater rapid thermal process (RTP) tool limits reaction to the surface of the wafer (10). Hydrogen is preferably added to improve the electrical properties of the oxide (14).

    摘要翻译： N2O用作形成超薄氧化物的氧化剂（14）。 与O2相比，N2O的低氧化效率允许氧化温度升高至大于850℃，同时保持生长速率。 冷壁灯加热器快速热处理（RTP）工具限制了对晶片（10）的表面的反应。 优选加入氢以改善氧化物（14）的电性能。

    Plasma process for organic residue removal from copper
    35.
    发明授权
    Plasma process for organic residue removal from copper 有权
    从铜中去除有机残留物的等离子体工艺

    公开(公告)号：US06342446B1

    公开(公告)日：2002-01-29

    申请号：US09407418

    申请日：1999-09-29

    申请人： Patricia B. Smith ,  Antonio L. P. Rotondaro

    发明人： Patricia B. Smith ,  Antonio L. P. Rotondaro

    IPC分类号： H01L2144

    CPC分类号： H01L21/76838 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76814

    摘要： An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the semiconductor substrate, the conductive structure comprised of an oxygen-sensitive conductor and having an exposed surface; oxidizing a portion of the conductive structure (step 313 of FIG. 1); and subjecting the conductive structure to a plasma which incorporates hydrogen or deuterium (step 315 of FIG. 1).

    摘要翻译： 本发明的一个实施例是一种制造形成在半导体晶片上的电子器件的方法，该方法包括以下步骤：在半导体衬底上形成导电结构，该导电结构由氧敏导体组成并具有暴露的 表面; 氧化导电结构的一部分（图1的步骤313）; 并对导电结构进行掺入氢或氘的等离子体（图1的步骤315）。

    Selectively self-assembling oxygen diffusion barrier
    37.
    发明授权
    Selectively self-assembling oxygen diffusion barrier 有权
    选择性地自组装氧扩散阻挡层

    公开(公告)号：US08410559B2

    公开(公告)日：2013-04-02

    申请号：US12407007

    申请日：2009-03-19

    申请人： Zhengwen Li ,  Antonio L. P. Rotondaro ,  Mark R. Visokay

    发明人： Zhengwen Li ,  Antonio L. P. Rotondaro ,  Mark R. Visokay

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/3105 ,  H01L21/3121 ,  H01L21/76224 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518

    摘要： A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.

    摘要翻译： 在与有源半导体区域相邻的半导体衬底中形成浅沟槽隔离结构。 在包括电介质氧化物材料的浅沟槽隔离结构的表面上形成选择性自组装氧阻挡层。 选择性自组装氧阻挡层的形成是选择性的，因为它不在具有半导体表面的有源半导体区域的表面上形成。 选择性自组装氧阻挡层是化学品的自组装单体层，其是包括至少一个亚烷基部分的烷基硅烷的衍生物。 化学式的含硅部分形成聚硅氧烷，其通过Si-O-Si键与表面硅烷醇基团键合。 化学品的单层是选择性自组装氧阻挡层，其防止氧扩散到随后沉积为栅极电介质的高介电常数材料层。

    BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE
    39.
    发明申请
    BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE 有权
    具有降低PARASITIC电容的身体接触晶体管

    公开(公告)号：US20110163382A1

    公开(公告)日：2011-07-07

    申请号：US12652364

    申请日：2010-01-05

    申请人： Antonio L. P. Rotondaro

    发明人： Antonio L. P. Rotondaro

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/78615

    摘要： A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (Å). This results in a lower parasitic capacitance at the body contact region.

    摘要翻译： 提供了一种接触绝缘体上半导体（SOI）金属栅极的晶体管，其具有降低的寄生栅极电容，其中栅极堆叠的金属部分在主体接触区域上被去除，并且形成接触的含硅材料 在SOI衬底的体接触区域中的栅极电介质。 这导致在身体接触区域上的有效栅极电介质厚度增加大于5埃（Å）。 这导致在身体接触区域的较低的寄生电容。

    Semiconductor device manufactured using a laminated stress layer
    40.
    发明授权
    Semiconductor device manufactured using a laminated stress layer 有权
    使用层压应力层制造的半导体器件

    公开(公告)号：US07611939B2

    公开(公告)日：2009-11-03

    申请号：US11745044

    申请日：2007-05-07

    申请人： Manoj Mehrotra ,  Antonio L. P. Rotondaro ,  Puneet Kohli

    发明人： Manoj Mehrotra ,  Antonio L. P. Rotondaro ,  Puneet Kohli

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

    摘要翻译： 提出了形成半导体器件的方法。 该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。 在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底之上形成层压应力层。 层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。 在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。