公开(公告)号：US20150309939A1

公开(公告)日：2015-10-29

申请号：US14263369

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Brian P. Lilly ,  Hari S. Kannan

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

Abstract translation: 用于选择性地降低高速缓存存储器的一部分的方法和装置包括根据对高速缓冲存储器的访问次数确定掉电条件。 响应于断电状态的检测，根据还包括在另一个高速缓冲存储器中的每种高速缓存方式中的高速缓存行数量，选择包括在高速缓冲存储器中的一组高速缓存路。 该方法还包括锁定和刷新所选择的一组高速缓存路径，然后激活所选择的高速缓存路径组的低功率模式。

公开(公告)号：US20140195737A1

公开(公告)日：2014-07-10

申请号：US13734444

申请日：2013-01-04

Applicant: APPLE INC.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Techniques are disclosed related to flushing one or more data caches. In one embodiment an apparatus includes a processing element, a first cache associated with the processing element, and a circuit configured to copy modified data from the first cache to a second cache in response to determining an activity level of the processing element. In this embodiment, the apparatus is configured to alter a power state of the first cache after the circuit copies the modified data. The first cache may be at a lower level in a memory hierarchy relative to the second cache. In one embodiment, the circuit is also configured to copy data from the second cache to a third cache or a memory after a particular time interval. In some embodiments, the circuit is configured to copy data while one or more pipeline elements of the apparatus are in a low-power state.

Abstract translation: 公开了涉及冲洗一个或多个数据高速缓存的技术。 在一个实施例中，设备包括处理元件，与处理元件相关联的第一高速缓存器，以及被配置为响应于确定处理元件的活动级别将修改的数据从第一高速缓存复制到第二高速缓存的电路。 在该实施例中，该装置被配置为在电路复制修改的数据之后改变第一高速缓存的功率状态。 第一缓存可以在相对于第二高速缓存的存储器层级中处于较低级。 在一个实施例中，电路还被配置为在特定时间间隔之后将数据从第二高速缓存复制到第三高速缓存或存储器。 在一些实施例中，电路被配置为在设备的一个或多个流水线元件处于低功率状态时复制数据。

公开(公告)号：US11947457B2

公开(公告)日：2024-04-02

申请号：US18058105

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US11768690B2

公开(公告)日：2023-09-26

申请号：US17532072

申请日：2021-11-22

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Brian P. Lilly ,  James Vash ,  Jason M. Kassoff ,  Krishna C. Potnuru ,  Rajdeep L. Bhuyar ,  Ran A. Chachick ,  Tyler J. Huberty ,  Derek R. Kumar

IPC: G06F9/38 ,  G06F11/30 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/3877 ,  G06F9/3009 ,  G06F9/3836 ,  G06F9/3863 ,  G06F9/3881 ,  G06F9/4887 ,  G06F11/3024 ,  G06F9/3879

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

公开(公告)号：US20230169003A1

公开(公告)日：2023-06-01

申请号：US18160575

申请日：2023-01-27

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US11210104B1

公开(公告)日：2021-12-28

申请号：US17018963

申请日：2020-09-11

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Brian P. Lilly ,  James Vash ,  Jason M. Kassoff ,  Krishna C. Potnuru ,  Rajdeep L. Bhuyar ,  Ran A. Chachick ,  Tyler J. Huberty ,  Derek R. Kumar

IPC: G06F9/38 ,  G06F11/30 ,  G06F9/48 ,  G06F9/30

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

公开(公告)号：US09454486B2

公开(公告)日：2016-09-27

申请号：US13940525

申请日：2013-07-12

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Perumal R Subramoniam ,  Prashant Jain

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/6022 ,  G06F2212/654

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured to receive a request for a first cache line from a pre-fetch engine, and store the received request in an entry of the pending request buffer. The control circuit may be further configured to receive a request for a second cache line from a processor, and store the request received from the processor in the entry of the pending request buffer in response to a determination that the second cache line is the same as the first cache line.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括未决请求缓冲器和控制电路。 待决请求缓冲器可以包括多个缓冲器条目。 控制电路可以耦合到未决请求缓冲器，并且可以被配置为从预取引擎接收对第一高速缓存行的请求，并将接收到的请求存储在待处理请求缓冲器的条目中。 控制电路还可以被配置成从处理器接收对第二高速缓存行的请求，并且响应于第二高速缓存行与第二高速缓存行的相同的确定，将从处理器接收的请求存储在待处理请求缓冲器的条目中 第一个缓存行。

公开(公告)号：US09298620B2

公开(公告)日：2016-03-29

申请号：US14088980

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Hari S. Kannan ,  Brian P. Lilly ,  Perumal R. Subramoniam

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0891 ,  Y02D10/13

Abstract: Systems, methods, and apparatuses for implementing selective victimization to reduce power and utilized bandwidth in a multi-level cache hierarchy. Each set of an upper-level cache includes a counter that keeps track of the number of times the set was accessed. These counters are periodically decremented by another counter that tracks the total number of accesses to the cache. If a given set counter is below a certain threshold value, clean victims are dropped from this given set instead of being sent to a lower-level cache. Also, a separate counter is used to track the total number of outstanding requests for the cache as a proxy for bus-bandwidth in order to gauge the total amount of traffic in the system. The cache will implement selective victimization whenever there is a large amount of traffic in the system.

Abstract translation: 用于实现选择性受害以在多级缓存层级中降低功率和利用带宽的系统，方法和装置。 每一组上级缓存包括一个计数器，用于跟踪该组被访问的次数。 这些计数器通过另一个计数器周期性递减，该计数器跟踪对高速缓存的总访问次数。 如果给定的设置计数器低于某个阈值，则清除的受害者将从该给定集合中删除，而不是发送到较低级别的缓存。 此外，使用单独的计数器来跟踪作为总线带宽的代理的缓存的未完成请求的总数，以便测量系统中的总流量。 当系统中存在大量流量时，缓存将实现选择性受害。

公开(公告)号：US09176879B2

公开(公告)日：2015-11-03

申请号：US13946327

申请日：2013-07-19

Applicant: Apple Inc.

Inventor： Brian P. Lilly ,  Gerard R. Williams, III ,  Mahnaz Sadoughi-Yarandi ,  Perumal R. Subramonium ,  Hari S. Kannan ,  Prashant Jain

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/127 ,  G06F2212/1021

Abstract: A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.

Abstract translation: 用于从高速缓冲存储器中逐出高速缓存行的机制包括首先选择驱逐一组无效高速缓存行的最近最少使用的高速缓存行。 如果所有高速缓存行都有效，则选择驱逐，一组高速缓存行的最近最少使用的高速缓存行，其中该高速缓存行组中的高速缓存行也不存储在诸如L1高速缓存的更高级高速缓冲存储器中 。 最后，如果所有高速缓存行都是有效的，并且没有非包含的高速缓存行，则选择驱逐存储在高速缓冲存储器中的最近最少使用的高速缓存行。

公开(公告)号：US20150277541A1

公开(公告)日：2015-10-01

申请号：US14224773

申请日：2014-03-25

Applicant: Apple Inc.

Inventor： Prashant Jain ,  Brian P. Lilly ,  Mahnaz Sadoughi-Yarandi ,  Helen Huang

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3296 ,  G06F12/0802 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  G11C5/14 ,  G11C7/04 ,  G11C7/12 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.

Abstract translation: 降低SoC内二级缓存中漏电功率的系统和方法。 L2缓存分为多个银行，每个银行都有自己独立的电源。 为每个银行维护一个空闲计数器来计算银行已经不活动的周期数。 SoC的温度和泄漏因子用于选择SoC的工作点。 基于操作点，设置空闲计数器阈值，具有对应于相对低的空闲计数器阈值的高温度和高泄漏因子，以及对应于相对高的空闲计数器阈值的低温度和低泄漏因子。 当给定的空闲计数器超过空闲计数器阈值时，提供给相应存储体的电压降低到足以保留数据但不能访问的电压。