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    Modular Electrostatic Discharge (ESD) Protection
    31.
    发明申请
    Modular Electrostatic Discharge (ESD) Protection 有权
    模块化静电放电（ESD）保护

    公开(公告)号：US20160268248A1

    公开(公告)日：2016-09-15

    申请号：US14641486

    申请日：2015-03-09

    Applicant: Apple Inc.

    Inventor： Xiaofeng Fan ,  Xin Yi Zhang

    IPC: H01L27/02 ,  H01L23/50 ,  H01L23/60

    CPC classification number: H01L27/0255 ,  H01L23/552 ,  H01L23/60 ,  H01L27/0288 ,  H01L27/0292

    Abstract: In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

    Abstract translation: 在一个实施例中，集成电路（IC）可以包括耦合到IC的一个或多个引脚以在引脚上传送和/或接收电力的电路块。 电路块可以包括接地连接，其可以与集成电路的其它部件的接地连接电绝缘/电分离。 在一个实施例中，电路块可以包括用于耦合到引脚的焊盘的ESD保护电路。 IC可以包括用于焊盘的另一ESD保护电路。 电路块的ESD保护电路可以针对ESD事件在电路块内可能产生的电流的大小，并且IC的ESD保护电路的大小适合于可从IC的其他部件产生的电流。

    Curved Light Sensor
    34.
    发明申请
    Curved Light Sensor 审中-公开
    弯曲光传感器

    公开(公告)号：US20160050379A1

    公开(公告)日：2016-02-18

    申请号：US14462032

    申请日：2014-08-18

    Applicant: Apple Inc.

    Inventor： Tongbi T. Jiang ,  Xiaofeng Fan

    IPC: H04N5/372 ,  H04N5/225

    CPC classification number: H04N5/2253

    Abstract: An optical system can include a curved light sensor and an optical system positioned in front of the curved light sensor. The curved light sensor includes a substrate and a patterned stress film formed over at least surface of the substrate.

    Abstract translation: 光学系统可以包括弯曲光传感器和位于弯曲光传感器前面的光学系统。 弯曲光传感器包括基板和形成在基板的至少表面上的图案化应力膜。

    Vertically stacked image sensor
    35.
    发明授权
    Vertically stacked image sensor 有权
    垂直堆叠图像传感器

    公开(公告)号：US09245917B2

    公开(公告)日：2016-01-26

    申请号：US14324179

    申请日：2014-07-05

    Applicant: Apple Inc.

    Inventor： Xiaofeng Fan

    IPC: H01L27/146 ,  H04N9/04 ,  H01L29/78

    CPC classification number: H04N5/369 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14634 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14843 ,  H01L29/7827 ,  H04N5/335 ,  H04N9/045

    Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

    Abstract translation: 具有光电二极管芯片和晶体管阵列芯片的垂直堆叠图像传感器。 光电二极管芯片包括至少一个光电二极管，并且传输门从光电二极管芯片的顶表面垂直延伸。 图像传感器还包括堆叠在光电二极管芯片顶部的晶体管阵列芯片。 晶体管阵列芯片包括控制电路和存储节点。 图像传感器还包括垂直堆叠在晶体管阵列芯片上的逻辑芯片。 传输门将数据从至少一个光电二极管传送到晶体管阵列芯片，逻辑芯片选择性地激活垂直传输门，复位栅极，源极跟随器栅极和行选择栅极。

    Image Sensor Having Pixels with Different Integration Periods
    36.
    发明申请
    Image Sensor Having Pixels with Different Integration Periods 有权
    具有不同积分周期像素的图像传感器

    公开(公告)号：US20150163422A1

    公开(公告)日：2015-06-11

    申请号：US14098504

    申请日：2013-12-05

    Applicant: Apple Inc.

    Inventor： Xiaofeng Fan ,  Chiajen Lee ,  Michael R. Malone ,  Anup K. Sharma

    IPC: H04N5/353 ,  H04N5/378 ,  H04N5/355

    CPC classification number: H04N5/3535 ,  H04N5/35554

    Abstract: An image sensor includes pixels that accumulate charge during a first integration period and pixels that accumulate charge during shorter second integration periods when an image is captured. The pixels having the shorter second integration period accumulate charge at two or more different times during the first integration period. Charge is read out of the pixels associated with the first integration period at the end of the first integration period, while charge is read out of the pixels having the second integration period at the end of each second integration period.

    Abstract translation: 图像传感器包括在第一积分周期期间累积电荷的像素和当捕获图像的较短的第二积分周期期间累积电荷的像素。 具有较短的第二积分周期的像素在第一积分周期期间的两个或更多个不同时间积累电荷。 在第一积分周期结束时从与第一积分周期相关联的像素中读出电荷，同时在每个第二积分周期结束时从具有第二积分周期的像素中读出电荷。

    HYBRID IMAGE SENSOR
    37.
    发明申请
    HYBRID IMAGE SENSOR 有权
    混合图像传感器

    公开(公告)号：US20140267855A1

    公开(公告)日：2014-09-18

    申请号：US13797851

    申请日：2013-03-12

    Applicant: APPLE INC.

    Inventor： Xiaofeng Fan

    IPC: H04N5/369 ,  H01L27/148

    CPC classification number: H04N3/155 ,  H01L27/14609 ,  H01L27/14806 ,  H04N5/335 ,  H04N5/3575 ,  H04N5/37452 ,  H04N5/378

    Abstract: A method for performing correlated double sampling for a sensor, such as an image sensor. The method includes collecting a first charge corresponding to a first parameter, transferring the first charge to a first storage component, transferring the first charge from the first storage component to a second storage component, resetting the first storage component, transferring the first charge from the second storage component to the first storage component, and reading the first storage component to determine the first charge. The method may be implemented in electronic devices including image sensors.

    Abstract translation: 用于对诸如图像传感器的传感器执行相关双重采样的方法。 该方法包括收集对应于第一参数的第一电荷，将第一电荷转移到第一存储组件，将第一电荷从第一存储组件转移到第二存储组件，复位第一存储组件，将第一电荷从 第二存储组件到第一存储组件，以及读取第一存储组件以确定第一充电。 该方法可以在包括图像传感器的电子设备中实现。

    VERTICALLY STACKED IMAGE SENSOR
    38.
    发明申请
    VERTICALLY STACKED IMAGE SENSOR 有权
    垂直堆叠图像传感器

    公开(公告)号：US20140211056A1

    公开(公告)日：2014-07-31

    申请号：US13756459

    申请日：2013-01-31

    Applicant: APPLE INC.

    Inventor： Xiaofeng Fan

    IPC: H01L27/146 ,  H04N9/04

    CPC classification number: H04N5/369 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14634 ,  H01L27/14638 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14843 ,  H01L29/7827 ,  H04N5/335 ,  H04N9/045

    Abstract: A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.

    Abstract translation: 具有光电二极管芯片和晶体管阵列芯片的垂直堆叠图像传感器。 光电二极管芯片包括至少一个光电二极管，并且传输门从光电二极管芯片的顶表面垂直延伸。 图像传感器还包括堆叠在光电二极管芯片顶部的晶体管阵列芯片。 晶体管阵列芯片包括控制电路和存储节点。 图像传感器还包括垂直堆叠在晶体管阵列芯片上的逻辑芯片。 传输门将数据从至少一个光电二极管传送到晶体管阵列芯片，逻辑芯片选择性地激活垂直传输门，复位栅极，源极跟随器栅极和行选择栅极。

    Image sensor with a cross-wafer capacitator
    39.
    发明授权
    Image sensor with a cross-wafer capacitator 有权

    公开(公告)号：US11121165B2

    公开(公告)日：2021-09-14

    申请号：US15994874

    申请日：2018-05-31

    Applicant: Apple Inc.

    Inventor： Chiajen Lee ,  Xiaofeng Fan

    IPC: H01L27/14 ,  H01L27/146

    Abstract: One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.

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