公开(公告)号：US20210241807A1

公开(公告)日：2021-08-05

申请号：US16783104

申请日：2020-02-05

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C8/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

公开(公告)号：US10896707B2

公开(公告)日：2021-01-19

申请号：US16290822

申请日：2019-03-01

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Rahul Mathur ,  Cyrille Nicolas Dray ,  Yann Sarrazin ,  Julien Vincent Poitrat ,  Yannis Jallamion-Grive ,  Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight ,  Jonas {hacek over (S)}vedas

IPC: G11C8/00 ,  G11C11/00 ,  G11C11/16

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

公开(公告)号：US20200185014A1

公开(公告)日：2020-06-11

申请号：US16213832

申请日：2018-12-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Jungtae Kwon ,  Nicolaas Klarinus Johannes VAN WINKELHOFF

IPC: G11C8/10

Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.

公开(公告)号：US20190325950A1

公开(公告)日：2019-10-24

申请号：US15961862

申请日：2018-04-24

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.

公开(公告)号：US20190026417A1

公开(公告)日：2019-01-24

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US09891976B2

公开(公告)日：2018-02-13

申请号：US14633062

申请日：2015-02-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Gilbert Meyer ,  Vikas Chandra

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/08

CPC classification number: G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

公开(公告)号：US09721624B2

公开(公告)日：2017-08-01

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus Yeung ,  Fakhruddin Ali Bohra ,  Mudit Bhargava ,  Andy Wangkun Chen ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

公开(公告)号：US20170117022A1

公开(公告)日：2017-04-27

申请号：US15401588

申请日：2017-01-09

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC: G11C7/10 ,  G11C29/50 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

公开(公告)号：US20160064054A1

公开(公告)日：2016-03-03

申请号：US14836657

申请日：2015-08-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.

Abstract translation: 提供了一种操作存储器件的存储器件和方法。 存储器件包括被配置为接收存储器件的时钟信号的全局控制电路，并且存储器件配置为响应于时钟信号的单个边沿执行双存储器访问。 响应于时钟信号的单个边沿而产生用于双存储器存取的第一次访问的第一内部时钟脉冲和用于双存储器访问的第二访问的第二内部时钟脉冲。 全局控制电路根据由第一访问指示的第一组与由第二访问指示的第二组之间的比较产生比较信号，并且第二组的本地组控制电路被配置为产生第二内部时钟脉冲 依赖于比较信号。

公开(公告)号：US20160005448A1

公开(公告)日：2016-01-07

申请号：US14857527

申请日：2015-09-17

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

IPC: G11C8/12 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。