公开(公告)号：US11068268B2

公开(公告)日：2021-07-20

申请号：US16531208

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Nigel John Stephens ,  David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Matthew Lucien Evans

IPC: G06F9/30

Abstract: An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address-indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.

公开(公告)号：US11030344B2

公开(公告)日：2021-06-08

申请号：US16073497

申请日：2016-12-23

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F21/64 ,  G06F21/52 ,  G06F21/12 ,  G06F12/14 ,  G06F21/60

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus includes storage to store bounded pointers, where each bounded pointer comprises a pointer value and associated attributes, with the associated attributes including range information indicative of an allowable range of addresses when using the pointer value. Processing circuitry is used to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer. In addition, the associated attributes include signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed. Such an approach provides increase resilience to control flow integrity attack when using bounded pointers.

公开(公告)号：US10936504B2

公开(公告)日：2021-03-02

申请号：US15579665

申请日：2016-04-28

Applicant: ARM Limited

Inventor： Jason Parker ,  Richard Roy Grisenthwaite ,  Andrew Christopher Rose

IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/46 ,  G06F21/72 ,  G06F21/78 ,  G06F12/1036 ,  G06F12/14 ,  G06F12/1018

Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).

公开(公告)号：US10776120B2

公开(公告)日：2020-09-15

申请号：US15555239

申请日：2016-02-11

Applicant: ARM LIMITED

Inventor： Michael John Williams ,  John Michael Horley ,  Stephan Diestelhorst ,  Richard Roy Grisenthwaite

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

公开(公告)号：US10210349B2

公开(公告)日：2019-02-19

申请号：US13735350

申请日：2013-01-07

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC: G06F21/64 ,  G06F21/52 ,  G06F9/30 ,  G06F9/46

Abstract: A data processing apparatus has processing circuitry which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain.

公开(公告)号：US09983872B2

公开(公告)日：2018-05-29

申请号：US15666978

申请日：2017-08-02

Applicant: ARM Limited

Inventor： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US09940268B2

公开(公告)日：2018-04-10

申请号：US14762976

申请日：2013-02-05

Applicant: ARM LIMITED

Inventor： Simon John Craske ,  Richard Roy Grisenthwaite

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1458 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1416 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/651

Abstract: A processing apparatus has a memory protection unit (MPU) 38 and an address translation unit (ATU) 120 which operate concurrently for memory access operations performed by processing circuitry 22. The MPU 38 stores access permission data for corresponding regions of an address space. The ATU 120 stores address translation entries for defining virtual-to-physical mappings for corresponding pages of the address space. In response to a memory access operation specifying a target address, one of the MPU 38 and the ATU 120 is selected to handle the memory access operation based on the target address. If the MPU 38 is selected then the target address is a physical address and the MPU 38 checks access permissions using a corresponding set of permission data. If the ATU 120 is selected then the target address is a virtual address and is translated into a physical address using a corresponding translation entry.

公开(公告)号：US09477623B2

公开(公告)日：2016-10-25

申请号：US13960128

申请日：2013-08-06

Applicant: ARM LIMITED

Inventor： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/364

CPC classification number: G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

公开(公告)号：US08799621B2

公开(公告)日：2014-08-05

申请号：US13962139

申请日：2013-08-08

Applicant: ARM Limited

Inventor： Richard Roy Grisenthwaite

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F12/10 ,  G06F12/1009 ,  G06F2212/651

Abstract: Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.

Abstract translation: 存储器地址转换电路14执行自顶向下的页面行进操作，以使用存储在转换表28,32,36,38,40,40的层级中的转换数据将虚拟存储器地址VA转换为物理存储器地址PA。页面 大小变量S用于控制存储器地址转换电路14以不同尺寸的物理存储器地址页面，虚拟存储器地址和转换表的页面进行操作。 这些不同的大小可以是所有4 kB或全部64 kB。 该系统可以支持多个虚拟机执行环境。 这些虚拟机执行环境可以独立地设置自己的页面大小变量，以及相关联的管理程序62的页面大小。

公开(公告)号：US12197916B2

公开(公告)日：2025-01-14

申请号：US18006813

申请日：2021-07-08

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Matthew Lucien Evans ,  Jelena Milanovic

IPC: G06F9/30 ,  G06F9/38

Abstract: Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.