公开(公告)号：US20080017911A1

公开(公告)日：2008-01-24

申请号：US11798888

申请日：2007-05-17

申请人： Hiroshi Akahori ,  Wakako Takeuchi ,  Atsuhiro Sato

发明人： Hiroshi Akahori ,  Wakako Takeuchi ,  Atsuhiro Sato

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42336

摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

摘要翻译： 存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体 ，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

公开(公告)号：US20060281244A1

公开(公告)日：2006-12-14

申请号：US11447941

申请日：2006-06-07

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Atsuhiro Sato

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Atsuhiro Sato

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7883 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor memory device includes a semiconductor substrate. Two diffusion layers are separately arranged along a first direction on the surface of the semiconductor substrate and include impurities. Two element separation layers are separately arranged along a second direction in a surface of the semiconductor substrate and define an element region. A first insulating layer is disposed on the substrate. A first conductive layer is disposed on the first insulating layer between the two diffusion layers and between the two element separation layers. A second conductive layer is disposed on the first conductive layer and is smaller than the first conductive layer in the first direction and the second direction. A second insulating layer is disposed on the second conductive layer. A third conductive layer is disposed on the second insulating layer.

摘要翻译： 半导体存储器件包括半导体衬底。 两个扩散层沿着第一方向在半导体衬底的表面上分开排列并且包括杂质。 两个元件分离层在半导体衬底的表面中沿着第二方向分开布置并且限定元件区域。 第一绝缘层设置在基板上。 第一导电层设置在两个扩散层之间和两个元件分离层之间的第一绝缘层上。 第二导电层设置在第一导电层上，并且在第一方向和第二方向上小于第一导电层。 第二绝缘层设置在第二导电层上。 第三导电层设置在第二绝缘层上。

公开(公告)号：US20060131638A1

公开(公告)日：2006-06-22

申请号：US11337001

申请日：2006-01-23

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.

摘要翻译： 非易失性半导体存储器包括分别具有浮置栅极，控制栅极和栅极间绝缘膜的多个存储单元晶体管，其分别布置在相应的浮置栅极和相应的控制栅极之间，并沿着列方向展开; 以及沿着行方向以恒定间距部署的器件隔离区域，沿着列方向形成条纹图案。 控制栅极沿着行方向连续展开，并且栅极间绝缘膜沿列方向串联并沿行方向以恒定的间距彼此分离。

公开(公告)号：US20050199938A1

公开(公告)日：2005-09-15

申请号：US10971161

申请日：2004-10-25

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.

摘要翻译： 非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准 沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及 电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

公开(公告)号：US06798038B2

公开(公告)日：2004-09-28

申请号：US10140941

申请日：2002-05-09

申请人： Atsuhiro Sato ,  Masayuki Ichige ,  Seiichi Mori ,  Yuji Takeuchi ,  Hiroaki Hazama ,  Yukio Nishiyama ,  Hirotaka Ogihara ,  Naruhiko Kaji

发明人： Atsuhiro Sato ,  Masayuki Ichige ,  Seiichi Mori ,  Yuji Takeuchi ,  Hiroaki Hazama ,  Yukio Nishiyama ,  Hirotaka Ogihara ,  Naruhiko Kaji

IPC分类号： H01L2900

CPC分类号： H01L21/76224

摘要： Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

摘要翻译： 根据HDP技术，在形成在半导体衬底的表面上或上方的沟槽的内表面上开始形成第一氧化硅膜。 然后，第一氧化硅膜的沉积在沟槽的开口闭合之前停止。 此外，蚀刻沉积在开口附近的第一氧化硅膜，并且根据HDP技术在沉积在沟槽底部的第一氧化硅膜上形成第二氧化硅膜。 以这种方式，第一和第二氧化硅膜可以层压在沟槽的底部。

公开(公告)号：US08377814B2

公开(公告)日：2013-02-19

申请号：US13164931

申请日：2011-06-21

申请人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US08120092B2

公开(公告)日：2012-02-21

申请号：US12565181

申请日：2009-09-23

申请人： Atsuhiro Sato ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Fumitaka Arai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11529

摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.

摘要翻译： 存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。 第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。 第二选择晶体管的第三栅电极与第二电极相邻地形成。 在基板上形成周边晶体管的第四栅电极。 第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。 第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。 第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

公开(公告)号：US20100246255A1

公开(公告)日：2010-09-30

申请号：US12729626

申请日：2010-03-23

申请人： Yasuhiro SHIINO ,  Atsuhiro Sato ,  Takeshi Kamigaichi

发明人： Yasuhiro SHIINO ,  Atsuhiro Sato ,  Takeshi Kamigaichi

IPC分类号： G11C16/28

CPC分类号： G11C16/30 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  H01L27/11519 ,  H01L27/11521

摘要： A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.

摘要翻译： 非易失性半导体存储装置包括存储单元阵列和外围电路。 存储单元阵列包括沿第一方向延伸的有效区域，在第一方向上延伸的虚拟有源区域，多个有效区域上的存储单元，虚拟有效区域上的第一虚设单元，各自连接到对应存储器的扩散层区域 单元和对应的第一虚拟单元，在相应的有效区域中首先接触，并且在虚拟活动区域中的第二触点。 外围电路包括电压施加单元，其被配置为向每个第一触点施加第一电压，以将每个存储单元设置在写使能状态或第二电压以将存储单元设置在写禁止状态，并且应用 向第二接触器施加第三电压以改变虚设电池的阈值。

公开(公告)号：US07649221B2

公开(公告)日：2010-01-19

申请号：US11951026

申请日：2007-12-05

申请人： Makoto Sakuma ,  Atsuhiro Sato

发明人： Makoto Sakuma ,  Atsuhiro Sato

IPC分类号： H01L29/72

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.

摘要翻译： 非易失性半导体存储器包括：多个存储单元晶体管，其配置有分别布置在第一浮置栅极和第一控制栅极之间的第一浮动栅极，第一控制栅极和第一栅极间绝缘膜，并且它们对准 沿着位线方向; 器件隔离区沿着字线方向以恒定的间距设置，沿着位线方向形成条纹图案; 并且选择栅极晶体管，其设置在存储单元晶体管的对准的每一端，每个配置有第二浮置栅极，第二控制栅极，设置在第二浮置栅极和第二控制栅极之间的第二栅极间绝缘膜，以及 电连接到第二浮动栅极和第二控制栅极的侧壁栅极。

公开(公告)号：US07505312B2

公开(公告)日：2009-03-17

申请号：US11447963

申请日：2006-06-07

申请人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

发明人： Yasuhiko Matsunaga ,  Fumitaka Arai ,  Atsuhiro Sato ,  Makoto Sakuma ,  Masato Endo ,  Kiyohito Nishihara ,  Keiji Shuto ,  Naohisa Iino

IPC分类号： G11C16/10

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

摘要翻译： 公开了一种包括具有多个块的存储单元阵列的半导体集成电路器件，布置在存储单元阵列中并具有电荷存储层的第一非易失性半导体存储单元和第二非易失性半导体 存储单元，布置在与第一非易失性半导体存储单元相邻的存储单元阵列中，并具有电荷存储层。 在相对于第一非易失性半导体存储单元执行常规数据写入之后，相对于第二非易失性半导体存储单元执行正常数据写入。 在相对于第二非易失性半导体存储单元执行常规数据写入之后，相对于第一非易失性半导体存储单元执行附加数据写入。