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84 条记录 (耗时 0.031 秒)

    Method and apparatus for power mode transition in a multi-thread processor
    32.
    发明授权
    Method and apparatus for power mode transition in a multi-thread processor 失效
    多线程处理器中功率模式转换的方法和装置

    公开(公告)号：US06981163B2

    公开(公告)日：2005-12-27

    申请号：US10887488

    申请日：2004-07-07

    申请人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

    发明人： Bret L. Toll ,  Alan B. Kyker ,  Stephen H. Gunther

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/24 ,  Y02D50/20

    摘要： A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

    摘要翻译： 一种用于多线程处理器中功率模式转换的方法和装置。 发布第一指示，包括与处理器中的第一逻辑处理器相关联的第一标识符，第一逻辑处理器已经进入功率模式。 发出第二指示，包括与处理器中的第二逻辑处理器相关联的第二标识符，第二逻辑处理器已经进入电源模式。 指示可以是例如停止授权确认特殊总线周期，指示逻辑处理器已经进入停止许可模式。 当第一和第二指示都已被发出时，处理器可以转换到睡眠模式。

    Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem
    33.
    发明授权
    Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem 失效
    用于动态调整存储器子系统的功率/性能特性的方法和装置

    公开(公告)号：US5860106A

    公开(公告)日：1999-01-12

    申请号：US502094

    申请日：1995-07-13

    申请人： Stanley J. Domen ,  Dileep R. Idate ,  Stephen H. Gunther ,  George Thangadurai

    发明人： Stanley J. Domen ,  Dileep R. Idate ,  Stephen H. Gunther ,  George Thangadurai

    IPC分类号： G06F12/02 ,  G06F12/08 ,  G11C11/413 ,  G06F9/38 ,  G06F1/32

    CPC分类号： G11C11/413 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.

    摘要翻译： 一种用于动态调整存储器子系统的功率/性能特性的装置和方法。 由于存储器子系统访问要求在很大程度上取决于正在执行的应用程序，所以启用或禁用各个存储器系统组件（如现有技术中所使用的）的静态方法从功耗角度来看不是最佳的。 通过动态跟踪存储器子系统的行为，本发明预测下一个事件将具有某些特征的概率，例如它是否会导致需要高速缓冲存储器注意的存储器周期，该存储器周期是否会导致 高速缓冲存储器命中，以及如果请求的数据不在高速缓冲存储器的一个级别中，是否将在主存储器中命中DRAM页面。 基于这些概率，本发明动态地启用或禁用子系统的组件。 通过智能地调​​整这些组件的状态，可以实现显着的功率节省，而不会降低性能。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT
    35.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
    用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM

    公开(公告)号：US20150346804A1

    公开(公告)日：2015-12-03

    申请号：US14823994

    申请日：2015-08-11

    申请人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    发明人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  Y02D10/152

    摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

    摘要翻译： 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。

    Providing An Inter-Arrival Access Timer In A Processor
    38.
    发明申请
    Providing An Inter-Arrival Access Timer In A Processor 有权
    在处理器中提供访问间接访问计时器

    公开(公告)号：US20140149759A1

    公开(公告)日：2014-05-29

    申请号：US13685853

    申请日：2012-11-27

    申请人： Neena Conrad ,  Shaun M. Conrad ,  Stephen H. Gunther

    发明人： Neena Conrad ,  Shaun M. Conrad ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  G06F1/3228 ,  Y02D10/152

    摘要： In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the cores to control power consumption of the processor. In turn, the PCU includes a control logic to cause the processor to re-enter a first package low power state responsive to expiration of an inter-arrival timer, where this expiration indicates that a time duration subsequent to a transaction received in the processor has occurred. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到核心的功率控制单元（PCU），以控制处理器的功耗。 反过来，PCU包括控制逻辑，以使得处理器响应到达到达定时器的到期而重新进入第一包低功率状态，其中该到期指示在处理器中接收的事务之后的持续时间具有 发生。 描述和要求保护其他实施例。

    Dynamic voltage transitions
    39.
    发明授权
    Dynamic voltage transitions 有权
    动态电压转换

    公开(公告)号：US08719600B2

    公开(公告)日：2014-05-06

    申请号：US13600044

    申请日：2012-08-30

    申请人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    发明人： Stephen H. Gunther ,  Robert Greiner ,  Matthew M. Ma ,  Kevin Dai

    IPC分类号： G06F1/26 ,  H01L29/66

    CPC分类号： G06F1/26

    摘要： The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

    摘要翻译： 响应于一个或多个条件（例如，膝上型计算机连接到AC电源）来改变集成电路（例如，处理器）的工作电压。 集成电路的工作频率和工作电压均改变。 使得向集成电路提供工作电压的电压调节器使用一个或多个中间步骤在电压电平之间转变。 在新电压和整个电压转换期间，集成电路继续以正常方式工作。

    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT
    40.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT 有权
    用于能源效率和能源保护的方法，装置和系统，包括检测和控制处理电路中的电流RAM

    公开(公告)号：US20120221871A1

    公开(公告)日：2012-08-30

    申请号：US13340511

    申请日：2011-12-29

    申请人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    发明人： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3243 ,  Y02D10/152

    摘要： Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

    摘要翻译： 一些实施方案提供了用于调整由处理器执行操作的速率的技术和布置，其基于由执行第一组操作的结果和由处理器消耗的功率的第二指示来比较由处理器消耗的功率的第一指示 作为执行第二组操作的结果的处理器。 当比较指示处理器消耗的功率的第一指示与处理器消耗的功率的第二指示之间的差异大于阈值时，可以调整由处理器执行操作的速率。