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    Independent Control Of Processor Core Retention States
    3.
    发明申请
    Independent Control Of Processor Core Retention States 有权
    处理器核心保留状态的独立控制

    公开(公告)号：US20140189225A1

    公开(公告)日：2014-07-03

    申请号：US13729833

    申请日：2012-12-28

    申请人： Shaun M. Conrad ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Anant S. Deval ,  Sanjeev S. Jahagirdar

    发明人： Shaun M. Conrad ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  Anant S. Deval ,  Sanjeev S. Jahagirdar

    IPC分类号： G06F1/32 ,  G11C7/10

    CPC分类号： G06F1/3296 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/172

    摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器， 当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。 响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值 电压值，独立于第二电压调节器。 存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。 描述和要求保护其他实施例。

    Controlling Configurable Peak Performance Limits Of A Processor
    4.
    发明申请
    Controlling Configurable Peak Performance Limits Of A Processor 有权
    控制处理器的可配置峰值性能限制

    公开(公告)号：US20140181538A1

    公开(公告)日：2014-06-26

    申请号：US13724732

    申请日：2012-12-21

    申请人： Jeremy J. Shrall ,  Stephen H. Gunther ,  Krishnakanth V. Sistla ,  Ryan D. Wells ,  Shaun M. Conrad

    发明人： Jeremy J. Shrall ,  Stephen H. Gunther ,  Krishnakanth V. Sistla ,  Ryan D. Wells ,  Shaun M. Conrad

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3243 ,  G06F1/324 ,  G06F3/14 ,  Y02D10/152

    摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储 每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。 反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。 描述和要求保护其他实施例。

    CONSTRAINING PROCESSOR OPERATION BASED ON POWER ENVELOPE INFORMATION
    6.
    发明申请
    CONSTRAINING PROCESSOR OPERATION BASED ON POWER ENVELOPE INFORMATION 有权
    基于功率密度信息的约束处理器操作

    公开(公告)号：US20150095666A1

    公开(公告)日：2015-04-02

    申请号：US14039193

    申请日：2013-09-27

    申请人： Avinash N. Ananthakrishnan ,  Stephen H. Gunther ,  Jeremy J. Shrall

    发明人： Avinash N. Ananthakrishnan ,  Stephen H. Gunther ,  Jeremy J. Shrall

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3206 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/324 ,  G06F11/3024 ,  G06F11/3058 ,  Y02D10/126 ,  Y02D10/174

    摘要： In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括执行指令的至少一个核心和耦合到核心的功率控制器。 功率控制器可以包括功率包络控制逻辑以接收多个功率包络参数，并且使得处理器的功率消耗水平能够超过时间窗口的一部分的功率突发阈值。 该部分可以根据时间窗口的长度和占空比来确定，其中功率包络参数被编程用于包括处理器的系统，并且包括功率脉冲串阈值，时间窗口和占空比。 描述和要求保护其他实施例。

    Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias
    9.
    发明申请
    Dynamic Balancing Of Power Across A Plurality Of Processor Domains According To Power Policy Control Bias 有权
    根据电力政策控制偏差，跨多个处理器域的动态平衡功率

    公开(公告)号：US20140181545A1

    公开(公告)日：2014-06-26

    申请号：US13724798

    申请日：2012-12-21

    申请人： Jeremy J. Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther

    发明人： Jeremy J. Shrall ,  Jay D. Schwartz ,  Stephen H. Gunther

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/324 ,  Y02D10/126

    摘要： In an embodiment, a processor includes multiple domains including a core domain having at least one core to execute instructions and a graphics domain including at least one graphics engine to perform graphics operations and a power controller to control power consumption of the processor. The power controller may include a logic to receive an indication of a priority domain of the domains and to dynamically allocate power to the domains based on a power limit, one or more maximum domain frequency requests, and the priority domain indication. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括多个域，包括具有至少一个核的执行指令的核心域和包括至少一个图形引擎以执行图形操作的图形域，以及功率控制器来控制处理器的功耗。 功率控制器可以包括用于接收域的优先级域的指示并且基于功率限制，一个或多个最大域频率请求和优先级域指示来动态地向域分配功率的逻辑。 描述和要求保护其他实施例。