公开(公告)号：US11133363B2

公开(公告)日：2021-09-28

申请号：US16556342

申请日：2019-08-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ke Wang ,  Xinhong Lu ,  Hehe Hu ,  Wei Yang ,  Ce Ning

IPC: H01L27/32 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.

公开(公告)号：US11043514B2

公开(公告)日：2021-06-22

申请号：US16486990

申请日：2018-12-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Xinhong Lu

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L27/32

Abstract: A method of fabricating an array substrate, an array substrate, and a display device is disclosed. The array substrate comprises a display area and a wiring area. The display area is disposed with a first thin film transistor and a second thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor comprises first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove comprises a first sub-groove and a second sub-groove that are stacked. The method includes simultaneously forming the first vias and the first sub-groove, and simultaneously forming the second vias and the second sub-groove.

公开(公告)号：US10795478B2

公开(公告)日：2020-10-06

申请号：US16319982

申请日：2018-05-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenlin Zhang ,  Wei Yang ,  Ce Ning

IPC: G06F3/041 ,  H01L27/12

Abstract: Provided are an array substrate and preparation method therefor, and a display apparatus. The array substrate includes: a substrate, the substrate having a first TFT region, a touch control region and a second TFT region; a photosensitive PN junction, the photosensitive PN junction being provided in the touch control region; a first thin-film transistor, provided in the first TFT region, and electrically connected to the photosensitive PN junction; and a second thin-film transistor, provided in the second TFT region, and electrically connected to a pixel electrode.

公开(公告)号：US20180337245A1

公开(公告)日：2018-11-22

申请号：US15865793

申请日：2018-01-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xinhong Lu ,  Ke Wang ,  Wei Yang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/4908 ,  H01L21/02178 ,  H01L21/02252 ,  H01L21/31116 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78642

Abstract: A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode.

公开(公告)号：US20160315195A1

公开(公告)日：2016-10-27

申请号：US15086857

申请日：2016-03-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning ,  Wei Yang ,  Xiaohu Li

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/22 ,  H01L21/027 ,  H01L29/45 ,  H01L27/12 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/0274 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/22 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method comprises: forming a first gate metal pattern on a base substrate; forming a gate insulating layer, a first active layer pattern and a source-drain metal pattern on the base substrate on which the first gate metal pattern is formed; forming a first protective layer pattern and a through hole pattern on the base substrate on which the source-drain metal pattern is formed; and forming a second active layer pattern and a pixel electrode pattern on the base substrate on which the first protective layer pattern is formed. Embodiments of the present disclosure solve problems of poor display performance and high cost of the array substrate and achieve effects of improving the display performance and reducing the cost.

Abstract translation: 提供阵列基板及其制造方法以及显示装置。 该制造方法包括：在基底基板上形成第一栅极金属图案; 在其上形成有第一栅极金属图案的基底基板上形成栅极绝缘层，第一有源层图案和源极 - 漏极金属图案; 在其上形成有源极 - 漏极金属图案的基底基板上形成第一保护层图案和通孔图案; 以及在其上形成有第一保护层图案的基底基板上形成第二有源层图案和像素电极图案。 本公开的实施例解决了显示性能差和阵列基板的高成本的问题，并且实现了提高显示性能并降低成本的效果。

公开(公告)号：US09362414B2

公开(公告)日：2016-06-07

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke Wang ,  Seongyeol Yoo ,  Ce Ning ,  Wei Yang

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.

公开(公告)号：US20250164843A1

公开(公告)日：2025-05-22

申请号：US19027233

申请日：2025-01-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60

Abstract: A displaying base plate and a displaying device are provided by the present application, wherein the displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate.

公开(公告)号：US11646327B2

公开(公告)日：2023-05-09

申请号：US17328393

申请日：2021-05-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei Yang ,  Xinhong Lu

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1255 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78675 ,  H10K59/1213 ,  H10K59/1216

Abstract: A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.

公开(公告)号：US11283039B2

公开(公告)日：2022-03-22

申请号：US16956983

申请日：2020-02-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenlin Zhang ,  Wei Yang

IPC: H01L29/08 ,  H01L51/50 ,  H01L51/56

Abstract: The present disclosure relates to the field of display technology, and provides a display substrate, its manufacturing method, and a display device. The display substrate includes a display region and a GOA region. An active layer of a TFT at the GOA region at least includes a first oxide semiconductor layer and a second oxide semiconductor layer arranged on the first oxide semiconductor layer, and the first oxide semiconductor layer is arranged between the second oxide semiconductor layer and a base substrate of the display substrate and has a carrier mobility of smaller than the second oxide semiconductor layer.

公开(公告)号：US11257849B2

公开(公告)日：2022-02-22

申请号：US16531231

申请日：2019-08-05

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wei Yang ,  Guangcai Yuan ,  Ce Ning ,  Xinhong Lu

IPC: H01L29/10 ,  H01L27/12

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes: a base substrate; a first thin film transistor on one side of the base substrate, the first thin film transistor comprising: a first active layer, a first protection layer, a second protection layer, a first source and a first drain; wherein the first protection layer and the second protection layer are on one side of the first active layer away from the base substrate, and are separated from each other; the first protection layer and the second protection layer are configured to protect the first active layer from being etched during forming of a via-hole corresponding to the first source and/or a via-hole corresponding to the first drain.