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    Thin Film Transistor and Manufacturing Method Thereof, and Array Substrate and Electronic Device
    31.
    发明申请
    Thin Film Transistor and Manufacturing Method Thereof, and Array Substrate and Electronic Device 有权

    公开(公告)号：US20230015871A1

    公开(公告)日：2023-01-19

    申请号：US17780877

    申请日：2021-05-27

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Jie Huang ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Jiayu He ,  Nianqi Yao ,  Feng Qu ,  Xiaochun Xu

    IPC: H01L29/786 ,  H01L27/12

    Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and an electronic device arc provided. The thin film transistor includes an active layer including multiple oxide layers which includes a channel layer, a transition layer and a first barrier layer, the channel layer is an layer with a highest carrier mobility, the channel layer is a crystalline or amorphous oxide layer, the transition layer is in direct contact with the channel layer, the first barrier layer is an outermost oxide layer, the first barrier layer and the transition layer are both crystalline oxide layers; a crystallization degree of the first barrier layer and a crystallization degree of the transition layer are greater than a crystallization degree of the channel layer, and a band gap of the first barrier layer and a band gap of the transition layer are larger than a band gap of the channel layer.

    ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY PANEL
    33.
    发明申请
    ARRAY SUBSTRATE, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND DISPLAY PANEL 有权

    公开(公告)号：US20210217784A1

    公开(公告)日：2021-07-15

    申请号：US16761335

    申请日：2019-11-21

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Zhengliang Li ,  Jiayu He ,  Hehe Hu ,  Wenlin Zhang ,  Song Liu ,  Xiaochen Ma ,  Nianqi Yao ,  Jie Huang

    IPC: H01L27/144

    Abstract: An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes: a base substrate; a thin film transistor on the base substrate; and a PIN diode on a side of the thin film transistor away from the base substrate, in a direction running away the base substrate from the thin film transistor, the PIN diode including a first electrical conduction type semiconductor layer and an intrinsic semiconductor layer and a second electrical conduction type semiconductor layer stacked in sequence, wherein a material from which the first electrical conduction type semiconductor layer is made includes one or more of following materials: metal oxide, metal sulfide, metal selenide, metal nitride, metal phosphide, or metal arsenide.

    Manufacturing method of array substrate, array substrate and display device
    36.
    发明授权
    Manufacturing method of array substrate, array substrate and display device 有权

    公开(公告)号：US10141352B2

    公开(公告)日：2018-11-27

    申请号：US15325402

    申请日：2016-03-09

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Zhanfeng Cao ,  Feng Zhang ,  Bin Zhang ,  Xiaolong He ,  Zhengliang Li ,  Wei Zhang ,  Feng Guan ,  Jincheng Gao

    IPC: H01L27/12 ,  H01L21/77

    Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

    MICRO-NANO FLUIDIC SUBSTRATE, CHIP, PREPARATION METHOD AND SYSTEM
    39.
    发明公开
    MICRO-NANO FLUIDIC SUBSTRATE, CHIP, PREPARATION METHOD AND SYSTEM 审中-公开

    公开(公告)号：US20240261785A1

    公开(公告)日：2024-08-08

    申请号：US18018795

    申请日：2021-12-31

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Feifei Li ,  Bolin Fan ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Nianqi Yao ,  Jiayu He ,  Jie Huang ,  Kun Zhao

    IPC: B01L3/00

    CPC classification number: B01L3/502761 ,  B01L2200/0647 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0848 ,  B01L2400/0415

    Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.

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