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    Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
    33.
    发明授权
    Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 失效
    制造由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区域的方法

    公开(公告)号：US5899727A

    公开(公告)日：1999-05-04

    申请号：US642155

    申请日：1996-05-02

    申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76205 ,  H01L21/76229

    摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

    摘要翻译： 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

    Method for forming semiconductor field region dielectrics having globally planarized upper surfaces
    34.
    发明授权
    Method for forming semiconductor field region dielectrics having globally planarized upper surfaces 失效
    用于形成具有全局平坦化的上表面的半导体场区电介质的方法

    公开(公告)号：US5830773A

    公开(公告)日：1998-11-03

    申请号：US634757

    申请日：1996-04-17

    申请人： William S. Brennan ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Mark W. Michael

    发明人： William S. Brennan ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Mark W. Michael

    IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/768 ,  H01L21/31

    CPC分类号： H01L21/76819 ,  H01L21/31055 ,  H01L21/76229

    摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.

    摘要翻译： 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。 因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。 当经受随后的蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率除去较高的高度区域。 因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。 在主要在较高高度区域蚀刻去除之后，将剩余的填充电介质上表面去除到与硅台面的上表面相当的水平，由此产生介于硅台面之间的单独的场电介质。 场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。 通过产生平面场电介质上表面，从形成在场电介质上或场电介质和硅台面之间的薄膜中去除了各种非平面性问题。

    Method of forming a recessed interconnect structure
    36.
    发明授权
    Method of forming a recessed interconnect structure 失效
    形成凹陷互连结构的方法

    公开(公告)号：US5767012A

    公开(公告)日：1998-06-16

    申请号：US660674

    申请日：1996-06-05

    申请人： H. Jim Fulford, Jr. ,  Basab Bandyopadhyay ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

    发明人： H. Jim Fulford, Jr. ,  Basab Bandyopadhyay ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L21/283

    CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L2924/0002

    摘要： A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.

    摘要翻译： 提供一种形成凹陷互连结构的方法。 互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。 在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。 通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。 形成凹陷互连结构的方法包括在半导体衬底上形成基本共面的第一导体组，在第一导体上沉积第一电介质层，在第一电介质层中形成沟槽，在沟槽中沉积导电材料， 对导电材料进行平面化，导电材料的上表面与第一电介质的上表面基本共面，蚀刻导电材料，直到导电材料的上表面位于第一电介质的上表面以下，形成第二电介质 在导电材料和第一介电层上。

    Photolithographic system including light filter that compensates for lens error
    40.
    发明授权
    Photolithographic system including light filter that compensates for lens error 有权
    光刻系统包括补偿透镜误差的滤光片

    公开(公告)号：US06552776B1

    公开(公告)日：2003-04-22

    申请号：US09183176

    申请日：1998-10-30

    申请人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

    发明人： Derick J. Wristers ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Mark W. Michael

    IPC分类号： G03B2754

    CPC分类号： G03F7/70558 ,  G03F7/70191 ,  G03F7/706

    摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.

    摘要翻译： 公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。