公开(公告)号：US07396767B2

公开(公告)日：2008-07-08

申请号：US10892915

申请日：2004-07-16

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Abstract translation: 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：US20060011996A1

公开(公告)日：2006-01-19

申请号：US10892915

申请日：2004-07-16

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66507 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908

Abstract: A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Abstract translation: 一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

公开(公告)号：US06365325B1

公开(公告)日：2002-04-02

申请号：US09247791

申请日：1999-02-10

Applicant: Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

Inventor： Min-Hsiung Chiang ,  Huan-Just Lin ,  James Cheng-Ming Wu ,  Cheng-Tung Lin

IPC: G03C500

CPC classification number: G03F7/40

Abstract: A method for fabricating a microelectronic layer. There is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture, where the first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer. The method is useful insofar as it allows the target layer to be fabricated while avoiding the use of advanced microelectronic fabrication photolithographic tooling when forming the patterned photoresist layer.

Abstract translation: 一种制造微电子层的方法。 首先提供基板。 然后在衬底上形成靶层。 然后在目标层上形成限定第一孔的图案化光致抗蚀剂层，其中第一孔具有暴露目标层的第一部分的第一孔宽度。 然后将图案化的光致抗蚀剂层热回流以形成限定基本上直的第二孔的回流图案化光致抗蚀剂层。 第二孔径具有小于第一孔径宽度的第二孔径宽度，并且第二孔口因此暴露了覆盖层目标层的面积尺寸小于覆盖层目标层的第一部分的第二部分。 最后，然后制造目标层以形成制造的目标层，同时使用回流图案化的光致抗蚀剂层作为掩模层。 该方法是有用的，只要它允许制造目标层，同时避免在形成图案化的光致抗蚀剂层时使用先进的微电子制造光刻工具。

公开(公告)号：US5536676A

公开(公告)日：1996-07-16

申请号：US415666

申请日：1995-04-03

Applicant: Huang-Chung Cheng ,  Cheng-Tung Lin ,  Chi-Hung Chao

Inventor： Huang-Chung Cheng ,  Cheng-Tung Lin ,  Chi-Hung Chao

IPC: H01L21/225 ,  H01L21/285 ,  H01L21/283

CPC classification number: H01L21/2257 ,  H01L21/28518

Abstract: A method for forming silicided shallow junctions, wherein impurities are implanted into a silicon layer formed over a silicon substrate. A metal layer selected from one of platinum (Pt), palladium (Pd), nickel (Ni) and cobalt (Co) is deposited over the silicon layer. At least one low temperature annealing process is carried out to form a silicide layer as well as the shallow junctions. Pre-anneal of the silicon layer and post-anneal of the silicide between 450.degree. and 600.degree. C. are also employed.

Abstract translation: 一种形成硅化浅结的方法，其中将杂质注入形成在硅衬底上的硅层中。 选自铂（Pt），钯（Pd），镍（Ni）和钴（Co）中的一种的金属层沉积在硅层上。 进行至少一个低温退火处理以形成硅化物层以及浅结。 还采用硅层的预退火和450℃至600℃之间的硅化物退火。

公开(公告)号：US07625801B2

公开(公告)日：2009-12-01

申请号：US11523678

申请日：2006-09-19

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

Abstract translation: 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

公开(公告)号：US20080299754A1

公开(公告)日：2008-12-04

申请号：US11809337

申请日：2007-05-31

Applicant: Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

Inventor： Chen-Hua Yu ,  Cheng-Tung Lin ,  Liang-Gi Yao

IPC: H01L21/3205

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer.

Abstract translation: 一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质上形成含金属层; 并在该含金属层上形成复合层。 形成复合层的步骤包括形成基本上不含p型和n型杂质的未掺杂硅层; 以及形成邻近所述未掺杂硅层的硅层。 形成硅层的步骤包括原位掺杂第一杂质。 （或者需要改变为：首先形成硅层，然后形成未掺杂的硅层）。该方法还包括执行退火以将硅层中的第一杂质扩散到未掺杂的硅层中。

公开(公告)号：US20060246720A1

公开(公告)日：2006-11-02

申请号：US11117152

申请日：2005-04-28

Applicant: Chii-Ming Wu ,  Shih-Wei Chou ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Shih-Wei Chou ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: A semiconductor method of manufacture involving suicides is provided. Embodiments comprise forming a stacked arrangement of layers, the stacked arrangement of layers comprising an additive layer on a substrate, and a metal layer on the additive layer, annealing the stacked arrangement of layers to form a metal silicide layer on the substrate, wherein the metal silicide layer includes an additive from the additive layer. Alternative embodiments include etching the stacked arrangement of layers to remove an unreacted material layer. In an alternative embodiment, the stacked arrangement of layer comprises a metal layer on a substrate, an additive layer on the metal layer, and an optional oxygen barrier layer on the additive layer. An annealing process forms a metal silicide containing an additive. Metal silicides formed according to embodiments are particularly resistant to agglomeration during high temperature processing.

Abstract translation: 提供涉及自杀的半导体制造方法。 实施例包括形成层的堆叠布置，在衬底上包括添加层的层的堆叠排列以及添加层上的金属层，退火层的层叠布置以在衬底上形成金属硅化物层，其中金属 硅化物层包括来自添加剂层的添加剂。 替代实施例包括蚀刻层的堆叠布置以去除未反应的材料层。 在替代实施例中，层的堆叠布置包括在基底上的金属层，金属层上的添加层和在添加剂层上的任选的氧阻隔层。 退火工艺形成含有添加剂的金属硅化物。 根据实施例形成的金属硅化物特别耐高温处理期间的附聚。

公开(公告)号：US20050272235A1

公开(公告)日：2005-12-08

申请号：US10859730

申请日：2004-06-03

Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Abstract translation: 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

Applicant: Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

Inventor： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC: C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC classification number: H01L21/28518 ,  C23C14/16

Abstract: A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

Abstract translation: 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US6042999A

公开(公告)日：2000-03-28

申请号：US73952

申请日：1998-05-07

Applicant: Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

Inventor： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76808 ,  G03F7/0035 ,  H01L21/0276

Abstract: A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

Abstract translation: 公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤 具有分隔下电介质层和上电介质层的蚀刻停止层的结构。 在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。 在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。 在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。