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229 条记录 (耗时 0.04 秒)

    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE
    31.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
    具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号：US20120098042A1

    公开(公告)日：2012-04-26

    申请号：US12911186

    申请日：2010-10-25

    申请人： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    发明人： Ming Cai ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/04

    CPC分类号： H01L21/2257 ,  H01L21/28512 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66643

    摘要： Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    摘要翻译： 公开了一种具有p-n结的半导体器件，其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说，形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层，并且将掺杂剂注入到金属硅化物层中。 执行退火处理，使掺杂剂朝向金属硅化物半导体层界面迁移，使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果，硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度，这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

    Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process
    33.
    发明申请
    Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process 有权
    碳纳米管/石墨烯CMOS单源自对准金属硅化物工艺的源/排水技术

    公开(公告)号：US20110253980A1

    公开(公告)日：2011-10-20

    申请号：US12762832

    申请日：2010-04-19

    申请人： Josephine B. Chang ,  Christian Lavoie ,  Zhen Zhang

    发明人： Josephine B. Chang ,  Christian Lavoie ,  Zhen Zhang

    IPC分类号： H01L29/775 ,  H01L21/336

    CPC分类号： H01L29/1606 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78618 ,  H01L29/78684 ,  H01L51/0048 ,  H01L51/105

    摘要： Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.

    摘要翻译： 提供了具有碳基材料的电子器件和用于与电子器件中的碳基材料接触的技术。 一方面，提供一种具有碳基材料的装置; 以及与包含金属硅化物，锗化锗或锗硅化物的碳基材料的至少一个电接触。 碳基材料可包括石墨烯或碳纳米管。 该装置还可以包括具有杂质的偏析区域，从金属硅化物，锗化锗或锗硅化物中分离碳基材料，其中该杂质具有不同于金属硅化物，锗化锗或锗硅酸盐的功函数 。 还提供了一种用于制造该装置的方法。

    Method for forming a protection layer over metal semiconductor contact and structure formed thereon
    35.
    发明授权
    Method for forming a protection layer over metal semiconductor contact and structure formed thereon 失效
    用于在金属半导体接触和其上形成的结构上形成保护层的方法

    公开(公告)号：US08030154B1

    公开(公告)日：2011-10-04

    申请号：US12849223

    申请日：2010-08-03

    申请人： Ahmet S. Ozcan ,  Christian Lavoie ,  Zhen Zhang ,  Bin Yang

    发明人： Ahmet S. Ozcan ,  Christian Lavoie ,  Zhen Zhang ,  Bin Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.

    摘要翻译： 在一个实施例中，提供了一种形成半导体器件的方法，其包括在半导体衬底上提供栅极结构。 侧壁间隔件可以与栅极结构相邻地形成。 可以在栅极结构的上表面和与栅极结构相邻的半导体衬底的暴露表面上形成金属半导体合金。 将金属半导体合金的上表面转化为含氧保护层。 使用对含氧保护层具有选择性的蚀刻来去除侧壁间隔物。 应变诱导层形成在栅极结构和半导体表面上，其中应变诱导层的至少一部分与栅极结构的侧壁表面直接接触。 在另一个实施方案中，金属半导体合金的含氧保护层通过两阶段退火工艺提供。

    Bipolar transistor with silicided sub-collector
    37.
    发明授权
    Bipolar transistor with silicided sub-collector 有权
    双极晶体管，带硅化子集电极

    公开(公告)号：US07679164B2

    公开(公告)日：2010-03-16

    申请号：US11620242

    申请日：2007-01-05

    申请人： Francois Pagette ,  Christian Lavoie ,  Anna Topol

    发明人： Francois Pagette ,  Christian Lavoie ,  Anna Topol

    IPC分类号： H01L27/102

    CPC分类号： H01L29/737 ,  H01L29/0821 ,  H01L29/66242

    摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.

    摘要翻译： 本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。 本发明的实施例还提供了制造该方法的方法。