公开(公告)号：US07851262B2

公开(公告)日：2010-12-14

申请号：US12270574

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/48 ,  H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的导电层上，使得芯片和图案化的阻焊层设置在图案化的导电层的两个相对的表面处。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成模塑料以封装图案化的导电层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US20090189296A1

公开(公告)日：2009-07-30

申请号：US12275172

申请日：2008-11-20

Applicant: Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

Inventor： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3114 ,  H01L23/49517 ,  H01L23/49822 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

Abstract translation: 提供了一种倒装芯片四边形扁平无铅封装结构的制造方法。 首先在制造方法中设置具有多根引线的引线框架。 在引线框架上形成介电层，并使引线的顶表面和底表面露出。 在电介质层上形成包括多个焊盘的重分配层和连接焊盘和引线顶表面的多条导线。 形成阻焊层以覆盖再分布层，电介质层和引线，并露出焊盘的表面。 在阻焊层上形成粘接层。 提供具有多个凸块的芯片。 该芯片用粘合剂层粘附在阻焊层上，并且每个凸块与其中一个焊盘电连接。

公开(公告)号：US20090068794A1

公开(公告)日：2009-03-12

申请号：US12270679

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供具有凹陷的导电层和导电层上的图案化阻焊层，其中图案化阻焊层覆盖导电层的凹部。 去除由图案化的阻焊层未覆盖的导电层的一部分，以便形成图案化的导电层。 芯片被结合到图案化的导电层上，使得图案化的阻焊层和芯片在图案化导电层的同一侧。 芯片通过接合线电连接到图案化导电层，其中芯片和接合线位于图案化导电层的相同侧。 形成至少一种模塑料，并分离模塑料和图案化的导电层。

公开(公告)号：US20090068792A1

公开(公告)日：2009-03-12

申请号：US12270602

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和图案化阻焊层的图案化导电层。 多个芯片被结合到图案化的导电层上，使得芯片和图案化的阻焊层设置在图案化的导电层的两个相对的表面处。 芯片通过穿过图案化导电层的第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US20090068789A1

公开(公告)日：2009-03-12

申请号：US12270574

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/00

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的导电层上，使得芯片和图案化的阻焊层设置在图案化的导电层的两个相对的表面处。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成模塑料以封装图案化的导电层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。

公开(公告)号：US20080315417A1

公开(公告)日：2008-12-25

申请号：US12201231

申请日：2008-08-29

Applicant: Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

Inventor： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

IPC: H01L23/498

CPC classification number: H01L24/83 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires.

Abstract translation: 芯片封装包括图案化导电层，第一阻焊层，第二阻焊层，芯片，接合线和模塑料。 图案化导电层具有彼此相对的第一表面和第二表面。 第一阻焊层设置在第一表面上。 第二阻焊层设置在第二表面上，其中第二表面的一部分被第二阻焊层曝光。 芯片设置在第一阻焊层上，其中第一阻焊层设置在图案化的导电层和芯片之间。 接合线电连接到芯片和由第二阻焊层暴露的图案化导电层。 模塑料封装图案导电层，第一阻焊层，第二阻焊层，芯片和接合线。

公开(公告)号：US07446400B2

公开(公告)日：2008-11-04

申请号：US11470494

申请日：2006-09-06

Applicant: Ya-Chi Chen ,  Chun-Ying Lin ,  Yu-Ren Chen ,  I-Hsin Mao

Inventor： Ya-Chi Chen ,  Chun-Ying Lin ,  Yu-Ren Chen ,  I-Hsin Mao

IPC: H01L23/495 ,  H01L23/04 ,  H01L23/48 ,  H01L23/50

CPC classification number: H01L23/4951 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.

Abstract translation: 提供了包括芯片，引线框架，第一接合线和第二接合线的芯片封装结构。 芯片具有有源表面，第一接合焊盘和第二接合焊盘，其中第一接合焊盘和第二接合焊盘设置在有源表面上。 芯片固定在引线框架下方，引线框架包括内部引线和母线。 内引线和母线设置在芯片的有效表面之上，并且母线位于内引线和相应的第一焊盘之间。 第一接合线分别连接第一接合焊盘和母线。 第二接合线分别连接母线和内引线的一部分。 第三接合线分别连接第二接合焊盘和另一个内部引线。

公开(公告)号：US20080265397A1

公开(公告)日：2008-10-30

申请号：US11872205

申请日：2007-10-15

Applicant: Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

Inventor： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC: H01L23/49

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US20080244457A1

公开(公告)日：2008-10-02

申请号：US11778240

申请日：2007-07-16

Applicant: Sheng-En Tang ,  Tsai-Chung Wang ,  Chun-Ying Lin

Inventor： Sheng-En Tang ,  Tsai-Chung Wang ,  Chun-Ying Lin

IPC: G06F3/048

CPC classification number: G06F3/0482

Abstract: A display device includes a display screen and a directional element. The display screen includes a first display area and a second display area. The directional element transmits a first trigger signal and a second trigger signal. The first trigger signal informs the first display area to display a directory menu, and the second trigger signal selects an option of the directory menu, so that the second display area can display a sub directory menu corresponding to the selected option. A method of displaying menus on a display device is also disclosed.

Abstract translation: 显示装置包括显示屏和定向元件。 显示屏包括第一显示区和第二显示区。 定向元件发送第一触发信号和第二触发信号。 第一触发信号通知第一显示区域显示目录菜单，第二触发信号选择目录菜单的选项，使得第二显示区域可以显示与所选择的选项相对应的子目录菜单。 还公开了在显示装置上显示菜单的方法。

公开(公告)号：US20080113049A1

公开(公告)日：2008-05-15

申请号：US11892630

申请日：2007-08-24

Applicant: Chia-Li Wei ,  Meng-Hwan Lee ,  Chun-Ying Lin ,  Jay Hua ,  Ying-Chieh Tsai

Inventor： Chia-Li Wei ,  Meng-Hwan Lee ,  Chun-Ying Lin ,  Jay Hua ,  Ying-Chieh Tsai

IPC: A61K36/00 ,  A61P21/02

CPC classification number: A61K36/45 ,  Y10S514/899

Abstract: A method for treating/relief of women's menstruation pain. The pain is reduced or relieved by externally administering an effective amount of an essential oil obtained from anthopogon.

Abstract translation: 治疗/缓解妇女月经痛的方法。 通过外用给予有效量的从anthopogon获得的精油减轻或减轻疼痛。