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31.发明授权Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions 有权将嵌入式存储器阵列中的BIST功能分割成远程低速可执行指令和本地较高速可执行指令的方法公开(公告)号：US07472325B2
公开(公告)日：2008-12-30
申请号：US12062599
申请日：2008-04-04
CPC分类号： G11C29/14 , G01R31/31724 , G01R31/3187 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
摘要翻译： 公开了一种用于将嵌入式存储器阵列的混合内置自检（BIST）架构的功能分割成远程低速可执行指令和本地较高速可执行指令的方法。 独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。 一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。 高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。 独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。
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32.发明授权Automatic shutdown or throttling of a bist state machine using thermal feedback 失效使用热反馈自动关闭或调节双速状态机公开(公告)号：US07458000B2
公开(公告)日：2008-11-25
申请号：US11278238
申请日：2006-03-31
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。
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33.发明申请HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN ASSOCIATED METHOD 有权用于嵌入式存储器阵列和相关方法的混合内置自检（BIST）架构公开(公告)号：US20080178053A1
公开(公告)日：2008-07-24
申请号：US12057405
申请日：2008-03-28
CPC分类号： G01R31/31724 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed are embodiments of a built-in self-test (BIST) architecture that incorporates a standalone controller that operates at a lower frequency to remotely perform test functions common to a plurality of embedded memory arrays. The architecture also incorporates command multipliers that are associated with the embedded memory arrays and that selectively operate in one of two different modes: a normal mode or a bypass mode. In the normal mode, instructions from the controller are multiplied so that memory array-specific test functions can be performed locally at the higher operating frequency of each specific memory array. Whereas, in the bypass mode, multiplication of the instructions is suspended so that memory array-specific test functions can be performed locally at the lower operating frequency of the controller. The ability to vary the frequency at which test functions are performed locally, allows for more test pattern flexibility.
摘要翻译： 公开了内置自检（BIST）架构的实施例，其包括以较低频率操作以远程执行多个嵌入式存储器阵列共同的测试功能的独立控制器。 该架构还包含与嵌入式存储器阵列相关联的命令乘法器，并且选择性地以两种不同模式之一操作：正常模式或旁路模式。 在正常模式下，来自控制器的指令相乘，使得存储器阵列特定的测试功能可以在每个特定存储器阵列的较高工作频率下本地执行。 而在旁路模式中，指令的乘法被暂停，使得可以在控制器的较低工作频率下本地执行存储器阵列特定的测试功能。 在本地执行测试功能的频率变化的能力允许更多的测试模式灵活性。
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公开(公告)号：US07194670B2
公开(公告)日：2007-03-20
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
发明人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。
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35.发明授权Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability 有权用于调整字线上电压的方法和系统，以提高相对于SRAM单元稳定性的产量公开(公告)号：US08582351B2
公开(公告)日：2013-11-12
申请号：US12892191
申请日：2010-09-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。
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36.发明申请公开(公告)号：US20130033951A1
公开(公告)日：2013-02-07
申请号：US13198894
申请日：2011-08-05
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译： 相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。 每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。 连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。 在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。
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公开(公告)号：US08239715B2
公开(公告)日：2012-08-07
申请号：US12144686
申请日：2008-06-24
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译： 提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。 该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。 在测试模式下，数据由LSSD_C时钟启动。 在功能模式下，数据由系统时钟（CLK）发送到RAM。 还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。
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公开(公告)号：US20110029827A1
公开(公告)日：2011-02-03
申请号：US12511739
申请日：2009-07-29
CPC分类号： G11C29/14
摘要： In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.
摘要翻译： 在一个实施例中，本发明是用于集成电路芯片中的嵌入式存储器的内置自检的方法，装置和设计结构。 用于嵌入式存储器的内置自检的方法的一个实施例包括以测试时钟的速度设置多个测试图案，其中测试时钟的速度足够慢以使测试者直接与一个 芯片，其中嵌入存储器，并且其中的设置包括将用于将测试图案传送到内置自检系统的一个或多个组件的多个信号状态，将测试图案作为 高速微冲速，以速度从嵌入式存储器捕获输出数据，输出数据仅对应于测试模式之一，并且以测试时钟的速度将输出数据与期望数据进行比较。
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39.发明授权Automatic shutdown or throttling of a BIST state machine using thermal feedback 失效使用热反馈自动关闭或调节BIST状态机公开(公告)号：US07689887B2
公开(公告)日：2010-03-30
申请号：US11962781
申请日：2007-12-21
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构 提供了体现在机器可读介质中的状态机。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。
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公开(公告)号：US20090319841A1
公开(公告)日：2009-12-24
申请号：US12144703
申请日：2008-06-24
IPC分类号： G06F11/267 , G01R31/28 , G01R31/317
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。 在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。 在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于该数据将数据传播到数据处理单元。 功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。
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