公开(公告)号：US08183546B2

公开(公告)日：2012-05-22

申请号：US12712816

申请日：2010-02-25

Applicant: Deepak A. Ramappa

Inventor： Deepak A. Ramappa

IPC: G21K5/04

CPC classification number: H01J37/3171 ,  H01J37/3002 ,  H01J37/32412 ,  H01J37/32422 ,  H01J2237/04 ,  H01J2237/2482 ,  H01J2237/3171

Abstract: Ions are generated and directed toward a workpiece. A laser source generates a laser that is projected above the workpiece in a line. As the laser is generated, a fraction of the ions are blocked by the laser. This may enable selective implantation or modification of the workpiece. In one particular embodiment, the lasers are generated while ions are directed toward the workpiece and then stopped. Ions are still directed toward the workpiece after the lasers are stopped.

Abstract translation: 产生的离子产生并指向工件。 激光源产生在工件上方一条线上投射的激光。 当激光产生时，一部分离子被激光器阻挡。 这可以使得能够选择性地植入或修改工件。 在一个具体实施例中，激光器被产生，而离子被指向工件然后停止。 在激光停止后，离子仍然朝向工件。

公开(公告)号：US20110259408A1

公开(公告)日：2011-10-27

申请号：US13091289

申请日：2011-04-21

Applicant: Deepak A. Ramappa ,  Ludovic Godet

Inventor： Deepak A. Ramappa ,  Ludovic Godet

IPC: H01L31/06 ,  H01L31/0224 ,  H01L31/0376

CPC classification number: H01L21/00 ,  C23C14/042 ,  C23C14/48 ,  C23C16/02 ,  C23C16/04 ,  C23C16/50 ,  H01L31/0682 ,  H01L31/0747 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of patterning a substrate includes providing a focusing plate adjacent to a plasma chamber containing a plasma, the focusing plate configured to extract ions from the plasma through at least one aperture that provides focused ions towards the substrate. The method further includes directing first ions through the at least one aperture to one or more first regions of the substrate so as to condense first gaseous species provided in ambient of the substrate on the one or more first regions of the substrate.

Abstract translation: 图案化衬底的方法包括提供邻近包含等离子体的等离子体室的聚焦板，该聚焦板被配置为通过至少一个孔向等离子体提取离子，所述孔向衬底提供聚焦离子。 该方法还包括将第一离子引导通过至少一个孔到基底的一个或多个第一区域，以便在衬底的一个或多个第一区域上冷凝在衬底环境中提供的第一气态物质。

公开(公告)号：US20110097840A1

公开(公告)日：2011-04-28

申请号：US12911029

申请日：2010-10-25

Applicant: Deepak A. Ramappa

Inventor： Deepak A. Ramappa

IPC: H01L31/18

CPC classification number: H01L31/1804 ,  H01L31/02168 ,  H01L31/022441 ,  H01L31/0682 ,  H01L31/1864 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods of improving the anti-reflection properties of one or more dielectric layers and reducing surface recombination of generated carriers of a solar cell are disclosed. In some embodiments, dopants are introduced into the dielectric layers to improve their anti-reflection properties. In other embodiments, species are introduced into the dielectric layers to create electrical fields which repel the minority carriers away from the surface and toward the contacts. In another embodiment, mobiles species are introduced to the anti-reflective coating, which cause carrier to be repelled from the surface of the solar cell. By creating a barrier at the surface of the solar cell, undesired recombination at the surface may be reduced.

Abstract translation: 公开了改善一个或多个电介质层的抗反射特性并减少太阳能电池的所生成的载流子的表面复合的方法。 在一些实施方案中，将掺杂剂引入电介质层以改善其抗反射性能。 在其它实施例中，物质被引入到电介质层中以形成电场，其排斥少数载流子远离表面并朝向接触。 在另一个实施方案中，将移动体物质引入到抗反射涂层中，这导致载体从太阳能电池的表面排斥。 通过在太阳能电池的表面产生阻挡层，可以减少表面处的不期望的复合。

公开(公告)号：US07902091B2

公开(公告)日：2011-03-08

申请号：US12538903

申请日：2009-08-11

Applicant: Deepak A. Ramappa

Inventor： Deepak A. Ramappa

IPC: H01L21/00

CPC classification number: H01L21/76254 ,  H01L21/26506 ,  H01L21/2658

Abstract: An improved process of substrate cleaving and a device to perform the cleaving are disclosed. In the traditional cleaving process, a layer of microbubbles is created within a substrate through the implantation of ions of a gaseous species, such as hydrogen or helium. The size and spatial distribution of these microbubbles is enhanced through the use of ultrasound energy. The ultrasound energy causes smaller microbubbles to join together and also reduces the straggle. An ultrasonic transducer is acoustically linked with the substrate to facilitate these effects. In some embodiments, the ultrasonic transducer is in communication with the platen, such that ultrasound energy can be applied during ion implantation and/or immediately thereafter. In other embodiments, the ultrasonic energy is applied to the substrate during a subsequent process, such as an anneal.

Abstract translation: 公开了一种改进的基板切割工艺和一种执行切割的装置。 在传统的切割过程中，通过注入气态物质如氢或氦的离子，在衬底内产生一层微泡。 这些微泡的尺寸和空间分布通过使用超声能量来增强。 超声波能量会导致较小的微泡连接在一起，并且还可以减少颤动。 超声换能器与衬底声学连接以促进这些效果。 在一些实施例中，超声波换能器与压板连通，使得在离子注入期间和/或之后立即施加超声波能量。 在其他实施例中，在后续工艺（例如退火）中将超声能量施加到衬底。

公开(公告)号：US07772867B2

公开(公告)日：2010-08-10

申请号：US12037687

申请日：2008-02-26

Applicant: Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

Inventor： Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

IPC: G01R31/02

CPC classification number: H01L22/14 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Abstract translation: 用于在半导体器件处理期间检测缺陷的方法可以包括提供具有电隔离应用的具有半导体层的衬底，并且在其上形成测试电路，将电子电流感应束引导到测试电路; 测量测试电路中的第一和第二接触焊盘之间的电流; 确定电子束感应电流（EBIC）; 以及基于EBIC和对应于EBIC的电子束的位置来识别测试电路中的一个或多个缺陷位置。 测试电路可以包括并联连接的多个半导体器件，耦合到半导体器件的第一端子的第一接触焊盘以及耦合到与半导体器件相关联的衬底端子的至少第二接触焊盘。

公开(公告)号：US07745238B2

公开(公告)日：2010-06-29

申请号：US12037531

申请日：2008-02-26

Applicant: Deepak A. Ramappa ,  Rosa A. Orozco-Teran ,  Laura Matz

Inventor： Deepak A. Ramappa ,  Rosa A. Orozco-Teran ,  Laura Matz

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/10

Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.

Abstract translation: 在半导体处理期间测量晶片温度的方法包括在处理步骤之间提供峰值晶片温度与处理步骤之后的晶片表面电荷或表面电位的变化之间的相关性的步骤。 通过处理步骤处理在处理步骤期间用于其峰值温度空间分布的特征的第一晶片。 在处理步骤之后测量在第一晶片上的多个位置处的晶片表面电荷或表面电位。 然后基于在测量步骤中测量的相关性和晶片表面电荷或表面电位来确定第一晶片的峰值温度空间分布。

公开(公告)号：US20090121353A1

公开(公告)日：2009-05-14

申请号：US11939040

申请日：2007-11-13

Applicant: Deepak A. Ramappa ,  Eden M. Zielinski

Inventor： Deepak A. Ramappa ,  Eden M. Zielinski

IPC: H01L21/768 ,  H01L23/52

CPC classification number: H01L23/522 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are methods of making semiconductor devices. The method can include forming a hard mask layer over a dielectric layer, forming a via through the hard mask layer and the dielectric layer, and depositing an anti-reflective coating in the via and over the hard mask layer. The method can also include etching a trench through the hard mask layer, etching a dummy fill pattern in the hard mask layer to a desired thickness, and etching the trench through the dielectric layer and the dummy fill through the hard mask layer and in the dielectric layer. The method can further include depositing copper in the via and in the trench and removing excess copper using chemical mechanical polishing, wherein the dummy fill in the dielectric layer is of desired reduced depth.

Abstract translation: 根据本发明，存在制造半导体器件的方法。 该方法可以包括在电介质层上形成硬掩模层，通过硬掩模层和介电层形成通孔，以及在通孔和硬掩模层上沉积抗反射涂层。 该方法还可以包括通过硬掩模层蚀刻沟槽，将硬掩模层中的虚拟填充图案蚀刻到期望的厚度，以及通过介电层蚀刻沟槽，并通过硬掩模层和电介质蚀刻沟槽 层。 该方法可以进一步包括在通孔和沟槽中沉积铜，并使用化学机械抛光去除多余的铜，其中介电层中的虚拟填充具有期望的减小的深度。

公开(公告)号：US20090087938A1

公开(公告)日：2009-04-02

申请号：US11863421

申请日：2007-09-28

Applicant: Deepak A. Ramappa ,  Richard L. Guldi

Inventor： Deepak A. Ramappa ,  Richard L. Guldi

IPC: H01L21/00

CPC classification number: H01L23/00 ,  B81C99/0055 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/97 ,  H01L2924/01006 ,  H01L2924/01082 ,  H01L2924/14

Abstract: Current manufacturing of miniature or micro electronic mechanical optical chemical or biophysical devices utilizes discrete substrates holding one or more said devices. The use of discrete substrates entails several disadvantages with respect to economical manufacturing. This invention is a method of manufacturing devices using flexible carrier sheets with device substrates attached to the carrier sheet, storage/transport devices for the carrier sheet, and process tools capable of continuous processing of the carrier sheets.

Abstract translation: 微型或微电子机械光学化学或生物物理器件的当前制造利用保持一个或多个所述器件的分立衬底。 使用分立的基板在经济制造方面需要几个缺点。 本发明是一种制造使用柔性载体片的装置的方法，其具有连接到载体片的装置基底，用于载体片的存储/输送装置和能够连续处理载体片的加工工具。

公开(公告)号：US20090017564A1

公开(公告)日：2009-01-15

申请号：US12234820

申请日：2008-09-22

Applicant: Deepak A. Ramappa

Inventor： Deepak A. Ramappa

IPC: H01L21/66 ,  G01R31/26

CPC classification number: G01R31/307

Abstract: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image is obtained using a collection field that is stronger than an incident field. The method further comprises using (130) the voltage contrast image to determine a metal silicide defect in a microelectronic device. Other aspects of the present invention include an inspection system (200) for detecting metal silicide defects and a method of manufacturing an integrated circuit (300).

Abstract translation: 本发明提供一种检测微电子器件中的金属硅化物缺陷的方法。 该方法包括在检查工具的视野中定位（110）半导体衬底的一部分。 该方法还包括产生（120）该部分的电压对比度图像，其中使用比入射场强的收集场获得图像。 该方法还包括使用（130）电压对比图像来确定微电子器件中的金属硅化物缺陷。 本发明的其他方面包括用于检测金属硅化物缺陷的检查系统（200）和制造集成电路（300）的方法。

公开(公告)号：US20080299718A1

公开(公告)日：2008-12-04

申请号：US11757147

申请日：2007-06-01

Applicant: Ping Jiang ,  Deepak A. Ramappa

Inventor： Ping Jiang ,  Deepak A. Ramappa

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L21/76808 ,  H01L29/78

Abstract: A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In the single damascene process using trench pattern, a trench is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the via-first process, using a via pattern, the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the trench first process, using the via pattern the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the single damascene or either via-first or trench-first dual damascene embodiment, the capping layer is retained over the low-k dielectric layer on top surfaces of the trench into the metal processing, generally including CMP processing, wherein the CMP process removes at least a portion, and in one embodiment the entire, capping layer.

Abstract translation: 使用通孔或沟槽第一方法形成单个或双镶嵌互连结构的方法包括以下步骤：提供其上具有蚀刻停止层的衬底表面，蚀刻停止层上的低k电介质层，以及 在低k电介质层上的介电覆盖层。 在使用沟槽图案的单个镶嵌工艺中，通过覆盖层，低k电介质层和蚀刻停止层蚀刻沟槽以到达衬底表面。 在通孔第一工艺中，使用通孔图案，通过覆盖层，低k电介质层和蚀刻停止层蚀刻通孔以到达衬底表面。 在沟槽第一工艺中，使用通孔图案，通过覆盖层，低k电介质层和蚀刻停止层蚀刻通孔以到达衬底表面。 在单镶嵌或通过第一或第一沟槽的双镶嵌实施例中，覆盖层保留在沟槽顶表面上的低k介电层上，进入金属加工，通常包括CMP处理，其中CMP工艺移除 至少一部分，并且在一个实施方案中为整个封盖层。