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公开(公告)号：US20120260070A1
公开(公告)日：2012-10-11
申请号：US13422539
申请日：2012-03-16
IPC分类号： G06F9/30
CPC分类号： G06F9/38 , G06F9/3851 , G06F11/267
摘要： A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance parameters of individual program threads to generate performance values. Issue control circuitry 28 reads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitry 12 within the processor 4.
摘要翻译： 多线程处理器4交织来自不同程序线程的程序指令，以执行细粒度多线程。 线程性能监视电路30监视各个程序线程的性能参数以产生性能值。 问题控制电路28读取这些性能值，以确定当线程切换事件发生时下一个选择哪个程序线程处于活动状态。 测量的性能参数可以包括程序线程能够提供用于由处理器4内的执行电路12执行的程序指令的循环的比例。
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32.发明授权Apparatus and method for error correction of data values in a storage device 有权用于存储设备中的数据值的纠错的装置和方法公开(公告)号：US08190973B2
公开(公告)日：2012-05-29
申请号：US12004511
申请日：2007-12-21
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F11/1666 , G06F11/20 , G11C2029/0411
摘要： A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error. Thus, if any hard errors do occur during normal operation of the storage device, they can effectively be temporarily corrected through use of the error cache to ensure that the retry mechanism proceeds correctly.
摘要翻译： 提供了一种数据处理装置，其中处理单元通过读取访问请求访问存储与这些数据值相关联的数据值和错误数据的存储设备。 当处理单元访问存储设备中的数据值时，错误检测电路检测该数据值中是否存在错误，如果需要，错误检测电路校正读取的数据值。 具有至少一个入口的错误高速缓存存储校正后的替换数据值，将校正后的数据值分配给错误高速缓冲存储器的条目，以生成每个校正数据值，并重新执行读访问请求。 替换数据值优先于存储在存储设备中的数据值从错误缓存读取。 这样可以确保重试机制成功，无论错误是软错误还是硬错误。 因此，如果在存储设备的正常操作期间发生任何硬错误，则可以通过使用错误高速缓存来有效地暂时地修正它们，以确保重试机制正确地进行。
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公开(公告)号：US07941584B2
公开(公告)日：2011-05-10
申请号：US12382939
申请日：2009-03-26
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry responds receipt of a write access request to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value a counter. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry jses a combination of buffers aid counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.
摘要翻译： 提供了一种数据处理装置和方法，用于在由一个或多个从属装置处理的处理电路发出的一系列访问请求中执行危险检测。 请求包括由寻址的从设备执行的一个或多个写访问请求。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应接收写入访问请求以执行更新处理，以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果该更新过程覆盖另一待决写入访问请求的标识，则 增加计数值计数器。 危害检查电路然后响应于要由处理电路发出的访问请求的至少一个子集，以参考未决的写入访问历史存储，以便确定是否发生危险状况。 更新电路以缓冲器组合的方式辅助计数器以保持每个未决写入访问请求的记录提供了相对于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。
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34.发明授权Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权用于处理由处理电路执行的指令的数据处理装置和方法公开(公告)号：US07925866B2
公开(公告)日：2011-04-12
申请号：US12314095
申请日：2008-12-03
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30149 , G06F9/3816 , G06F9/382 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。
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公开(公告)号：US07900019B2
公开(公告)日：2011-03-01
申请号：US11414547
申请日：2006-05-01
IPC分类号： G06F13/00
CPC分类号： G06F9/383 , G06F9/342 , G06F9/3832 , G06F12/0215 , G06F12/0292 , G06F12/06
摘要： A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logic (113) outputs a prediction indicating in which one of the plurality of memories a target data is stored. The target memory prediction logic (113) outputs the prediction in the same processing cycle as the output of the target memory address by the address generation logic (109). An associated method is also provided.
摘要翻译： 提供具有多个存储器的数据处理装置，其中地址生成逻辑（109）向多个存储器中的至少一个输出与要访问的数据相对应的目标存储器地址。 目标存储器预测逻辑（113）输出指示多个存储器中的哪个存储器存储目标数据的预测。 目标存储器预测逻辑（113）通过地址生成逻辑（109）在与目标存储器地址的输出相同的处理周期中输出预测。 还提供了相关联的方法。
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公开(公告)号：US20090313507A1
公开(公告)日：2009-12-17
申请号：US12155926
申请日：2008-06-11
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3636
摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.
摘要翻译： 提供了一种数据处理装置，其具有各自具有访问存储器的多个处理电路。 跟踪电路被提供用于产生跟踪数据流，用于产生对应于多个处理电路中的至少一个的跟踪数据流。 提供选择电路以使得跟踪电路的选择性切换不产生与多个处理电路中的第一个处理电路相对应的第一跟踪数据流，从而生成对应于多个处理电路中的不同处理电路的第二不同跟踪数据流。 根据与多个处理电路中的一个或多个相关联的处理状态信息执行选择性切换。 还提供了相应的方法和计算机程序产品。
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公开(公告)号：US07420970B2
公开(公告)日：2008-09-02
申请号：US10461879
申请日：2003-06-16
CPC分类号： H04J3/047
摘要： A read port for selectively coupling one of a plurality of inputs to an output is disclosed. The read port comprises: a plurality of inputs; an output; a plurality of multiplexers operable to selectively couple a selected input to said output; and a multiplexer control signal input for inputting a multiplexer control signal, the multiplexer control signal comprising a plurality of control parameters and being operable to control switching of the plurality of multiplexers. The plurality of multiplexers are arranged in a plurality of layers, the layers being arranged between the inputs and output, such that a selected input is operable to be coupled to the output via a multiplexer from each of the different layers. Furthermore, some of the layers are divided into portions, each portion having at least one control parameter input, so that each of the portions is operable to be controlled by a different one of the control parameters and multiplexers in one of the portions of a certain layers can be switched without switching multiplexers in another of the portions this layer. In some embodiments two outputs operable as two read ports are provided.
摘要翻译： 公开了用于选择性地将多个输入中的一个输入耦合到输出的读端口。 读取端口包括：多个输入; 输出 多个多路复用器，可操作以选择性地将所选输入耦合到所述输出; 以及多路复用器控制信号输入，用于输入多路复用器控制信号，所述多路复用器控制信号包括多个控制参数并且可操作以控制所述多个复用器的切换。 多个多路复用器被布置在多个层中，这些层被布置在输入和输出之间，使得所选择的输入可操作以经由来自每个不同层的多路复用器耦合到输出。 此外，一些层被分成部分，每个部分具有至少一个控制参数输入，使得每个部分可操作以由某一个的某个部分中的一个控制参数和多路复用器中的不同的一个来控制 可以切换层，而不需要在该层的另一部分中切换多路复用器。 在一些实施例中，提供可操作为两个读端口的两个输出。
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公开(公告)号：US07162611B2
公开(公告)日：2007-01-09
申请号：US10136346
申请日：2002-05-02
IPC分类号： G06F9/455
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30174 , G06F9/3816 , G06F9/3861 , G06F9/45504
摘要： Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.
摘要翻译： 检测到诸如Java字节码的第一指令集的程序指令的未处理操作。 代替调用用于直接处理该未处理操作的机制，代替使用来自第二指令集（诸如ARM指令）的一个或多个指令来模拟受未经处理的操作的指令。 如果第二指令集的这些指令也受到未处理的操作，则可以调用用于处理第二指令集内的未处理操作的机制来修复该操作。 该方法非常适用于处理具有本机固定长度指令集的处理器核心解释的可变长度指令的未处理操作。 特别地，可以以这种方式方便地处理预取中止和未处理的浮点操作。
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公开(公告)号：US08977820B2
公开(公告)日：2015-03-10
申请号：US12004476
申请日：2007-12-21
CPC分类号： G06F12/0864 , G06F11/1064 , G11C15/00 , G11C29/42 , G11C29/76 , G11C2029/0409 , G11C2029/0411
摘要： A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.
摘要翻译： 提供了一种用于处理在数据处理装置的高速缓存中出现的硬错误的数据处理装置和方法。 提供具有至少一个记录的缓存位置避免存储，其中每个记录用于存储标识特定高速缓存行的高速缓存行标识符。 在检测到错误状况时，分配缓存位置避免存储中的记录之一以存储与检测到错误条件的条目相关联的特定高速缓存行的高速缓存行标识符。 针对特定高速缓存线执行干净且无效的操作，然后重新执行访问请求。 缓存访问电路被布置为排除在高速缓存位置中识别的任何特定高速缓存行，避免存储从查找过程。
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公开(公告)号：US08498373B2
公开(公告)日：2013-07-30
申请号：US13348862
申请日：2012-01-12
申请人： John Michael Horley , Sheldon James Woodhouse , Michael John Williams , Sheshadri Kalkunte , Andrew Christopher Rose
发明人： John Michael Horley , Sheldon James Woodhouse , Michael John Williams , Sheshadri Kalkunte , Andrew Christopher Rose
IPC分类号： H03L7/00
摘要： A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.
摘要翻译： 计数值生成器包括用于接收同步计数值的输入，配置为以本地频率递增的计数器，本地频率比同步频率快;以及内插器，用于确定本地频率和同步频率之间的频率比 并且用于根据相对于频率比的计数器的最大值的相对量来确定计数器的增量值。 计数器产生包括表示整数值的预定位数的计数值，并输出为输出计数值的低位位和表示整数值的小数部分的附加低位位。 计数器包括用于输出同步计数值的输出电路和表示由计数器产生的整数值的预定位数作为计数值的低位位。
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